Skip to main content

Performance estimation of embedded software with pipeline and cache hazard modeling

  • II System Architecture
  • Conference paper
  • First Online:
High Performance Computing (ISHPC 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1336))

Included in the following conference series:

Abstract

A major challenge in telecommunication design is introducing flexibility while still meeting real-time performance goals. Keeping both flexibility and performance while minimizing cost, leads to mixed hardwaresoftware systems. In the absence of a generic partitioning algorithm, accurate cost and performance modeling become crucial when exploring architectural alternatives. This paper presents a case study in which we apply an efficient software performance estimation method to an ATM (Asynchronous Transfer Mode) network application. Since the execution efficiency of pipelined RISC machines heavily depends on the characteristics of the application and the underlying memory hierarchy, effects from pipeline- and cache stalls must be taken into account. The aim of our methodology is to increase the predictability of software execution time in order to minimize expensive hardware implementation.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Alles: ATM Internetworking. Cisco Systems Inc., 1995. http://cell-relay.indiana.edu/cell-relay/docs/cisco.html

    Google Scholar 

  2. E. Hoffman, A. Mankin and M. Perez: VINCE: Vendor Independent Network Control Entity. Naval Research Laboratory, 1993. ftp://hsdndev.harvard.edu/pub/mankin/

    Google Scholar 

  3. The ATM Forum: Traffic Management Specification Version 4. atmf95-0013R6, 1995.

    Google Scholar 

  4. K. Buchenrieder: Hardware/Software Codesign-An Annotated Bibliography. IT Press, Hartenstein, Chicago, 1995.

    Google Scholar 

  5. R. Gupta: Hardware-Software Co-design, Tools for Architecting Systems-On-AChip. Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 285–289, 1997.

    Google Scholar 

  6. W. Wolf: Hardware-Software Co-Design of Embedded Systems. Proc. of IEEE, Vol. 82, No.7, pp. 967–989, 1994.

    Google Scholar 

  7. W. Ye, R. Ernst, T. Brenner, and J. Henkel: Fast Timing Analysis for HardwareSoftware Co-Synthesis. Proc. of Int. Conf. Computer Design, IEEE CS Press, pp. 452–457, 1993.

    Google Scholar 

  8. Y-T. S. Li, S. Malik, and A. Wolfe: Performance Estimation of Embedded Software with Instruction Cache Modeling. Proc. of Int. Conf. on ComputerAided Design (ICCAD), pp. 380–387,1995.

    Google Scholar 

  9. The ATM Forum: An ATM-PHY Interface Specification Level 1. Version 2.01, 1997.

    Google Scholar 

  10. J. L. Hennessy and D. A. Patterson: Computer Architecture, A Quantitative Approach. Morgan Kaufmann Publishers Inc., Second Edition, 1996.

    Google Scholar 

  11. M. Inamori, K. Ishii, A. Tsutsui, K. Shirakawa, and T. Miyazaki: A New Processor Architecture for Digital Signal Transport Systems, to appear in Proc. of ICCD, 1997.

    Google Scholar 

  12. L. B. Hostetler, B. Mirtich: DLXsim-A Simulator for DLX. Reference Manual, 1996. ftp://max.stanford.edu/pub/hennessy-patterson. software

    Google Scholar 

  13. M. D. Hill: Cache simulator dineroIIl. Reference Manual, 1989. ftp://max.stanford.edu/pub/hennessy-patterson.software

    Google Scholar 

  14. Y. Nakamura, K. Oguri, A. Nagoya, M. Yukishita, R. Nomura: High-Level Synthesis Design at NTT Systems Labs. MICE Trans. on Information and Systems, Vol. E76-D, No 9, pp. 1047–1054, 1993.

    Google Scholar 

  15. J. Suzuki and S. Ono: Entropy CODEC from Behavioral Description Based LSICAD for Fully Programmable Image Coding System. Proc. of Design Automation for Embedded Systems, pp. 231–255, 1996.

    Google Scholar 

  16. Y. Nakamura, K. Oguri, A. Nagoya, and R. Nomura: A hierarchical behavioral description based CAD System. Proc. of EURO ASIC, pp. 282–287, 1990.

    Google Scholar 

  17. Xilinx: The programmable Logic Data Book. Xilinx Inc., 1994.

    Google Scholar 

  18. N. Ohta, H. Nakada, K. Yamada, A. Tsutsui, and T. Miyazaki: PROTEUS: Programmable Hardware for Telecommuncication Systems. Proc. of ICCD, 1994.

    Google Scholar 

  19. Y. Takabatake, M. Hashimoto, T. Tsujita, J. Takeda, and Y. Shobatake: A Software-Based ATM Interface Card and its Evaluation. IEICE Trans. on Communications, Vol. E-80-B, No. 1, pp. 127–134, 1997.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Constantine Polychronopoulos Kazuki Joe Keijiro Araki Makoto Amamiya

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Imlig, N., Tsutsui, A. (1997). Performance estimation of embedded software with pipeline and cache hazard modeling. In: Polychronopoulos, C., Joe, K., Araki, K., Amamiya, M. (eds) High Performance Computing. ISHPC 1997. Lecture Notes in Computer Science, vol 1336. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0024211

Download citation

  • DOI: https://doi.org/10.1007/BFb0024211

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63766-0

  • Online ISBN: 978-3-540-69644-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics