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Logic verification of incomplete functions and design error location

  • Qinhai Zhang
  • Charles Trullemans
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 683)

Abstract

At the stage of logic verification, it is necessary not only to detect but also to locate the sources of design errors that may exist in the gate-level circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified to be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.

Keywords

Signal Line Design Error Binary Decision Diagram Fault Simulation Combinational Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Qinhai Zhang
    • 1
  • Charles Trullemans
    • 1
  1. 1.Laboratoire de MicroélectroniqueUniversité Catholique de LouvainLouvain-La-NeuveBelgium

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