The random testability of the n-input AND gate

Abstract

Probabilistic testing is very attractive due to the low test generation costs. Unfortunately, not all circuits are well random testable. To eliminate this deficiency, biased random testing has been adopted. We distinguish input signal biased (ISB) random testing, where a distribution different from the uniform one is achieved by giving each primary input an individual signal probability, from pattern biased (PB) random testing, which allows an arbitrary distribution for the input patterns.

An extreme example illustrating the poor conventional random testability is the n-input AND gate. It is shown that its expected test length is 2ⁿ · H _n+1, where H _n denotes the n ^th harmonic number. For PB random testability the optimal strategy is presented. It yields (n+1) · H ⁿ⁺¹ as expected test length. It is shown how the optimal signal probabilities for ISB random testing can be calculated on condition that the signal probabilities at all primary inputs are equal. Furthermore, e·n·H _n+1 (e=2.71 ...) is proved to be an upper bound for the best achievable expected test size by ISB random testing. Hence it follows that PB random testing is not much superior to ISB random testing for AND gates.