High-Speed Transmitter Designs for DDR3 SDRAM Memory Interfaces

  • Lim Zong ZhengEmail author
  • Mohd Tafir Mustaffa
  • Ch’ng Siew Sin
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 291)


This work presents two high-speed transmitter designs for 2.4 Gbps Double Data Rate Generation 3 (DDR3) memory interfaces. The transmitters are designed using 45-nm CMOS process. Moreover, output slew rate of both transmitters is controlled at 4–6 V/ns, while their output impedance can be programmed between 20, 30 and 40 Ω, respectively. Output slew rate and impedance of both the transmitters are calibrated across process, voltage and temperature (PVT) variations. A comparison between Multi-Module Transmitter (MMTX) and Single-Module Transmitter (SMTX) is also presented with low pad capacitance and small far-end eye jitter as the main figures of merit.


DDR3 Memory interface Multi-module transmitter Single-module transmitter 


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Copyright information

© Springer Science+Business Media Singapore 2014

Authors and Affiliations

  • Lim Zong Zheng
    • 1
    Email author
  • Mohd Tafir Mustaffa
    • 2
  • Ch’ng Siew Sin
    • 1
  1. 1.School of Electrical and Electronic EngineeringUniversiti Sains MalaysiaNibong TebalMalaysia
  2. 2.School of Electrical and Electronic EngineeringUniversiti Sains MalaysiaNibong TebalMalaysia

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