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User Guided Register Manipulation in Digital Circuits

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VLSI Design and Test (VDAT 2019)

Abstract

Retiming is a widely used optimization technique in any electronic design automation (EDA) tools. Retiming primarily moves registers in digital circuit to improve the timing of the circuit. Retiming does not always produce the desired result due to various factors. As a result, the designer sometimes needs to insert register(s) into specific location(s) or delete or move register(s) from specific location(s) in order to break critical paths. This task has to be done along with register balancing i.e. the designer also needs to add or delete or move registers in all parallel paths as well to keep the functionality of the design unchanged. Manual register balancing in all parallel paths is complex and error prone due to the complexity of the design. So, this task has to be automated. The proposed method in this paper automatically inserts or deletes or moves register(s) to or from user specified location(s) and also does the register balancing in all parallel paths automatically. A Python based implementation has also been presented for the proposed method.

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References

  1. Karfa, C.: Automatic register balancing in model-based high-level synthesis. In: 6th Asia Symposium on Quality Electronic Design, Kula Lumpur, pp. 43–49 (2015). https://doi.org/10.1109/ACQED.2015.7274005

  2. Malik, S., Sentovich, E.M., Brayton, R.K., Sangiovanni-Vincentelli, A.: Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 10(1), 74–84 (1991). https://doi.org/10.1109/43.62793

    Article  Google Scholar 

  3. Leiserson, C.E., Saxe, J.B.: Optimizing synchronous systems. In: 22nd Annual Symposium on Foundations of Computer Science, Nashville, TN, USA, pp. 23–36 (1981). https://doi.org/10.1109/SFCS.1981.34

  4. Leiserson, C.E., Saxe, J.B.: Retiming synchronous circuitry. Algorithmica 6(1), 5–35 (1991)

    Article  MathSciNet  Google Scholar 

  5. Shenoy, N.: Retiming: theory and practice. Integr. VLSI J. 22, 1–21 (1997)

    Article  Google Scholar 

  6. Ekpanyapong, M., Waterwait, T., Lim, S.K.: Statistical Bellman-Ford algorithm with an application to retiming. In: Asia and South Pacific Conference on Design Automation, Yokohama, p. 6 (2006). https://doi.org/10.1109/ASPDAC.2006.1594810

  7. Busato, F., Bombieri, N.: An efficient implementation of the Bellman-Ford algorithm for Kepler GPU architectures. IEEE Trans. Parallel Distrib. Syst. 27(8), 2222–2233 (2016). https://doi.org/10.1109/TPDS.2015.2485994

    Article  Google Scholar 

  8. Dongare, A.D., Kharde, R.R., Kachare, A.D.: Introduction to artificial neural network. Int. J. Eng. Innov. Technol. 2(1) (2012)

    Google Scholar 

  9. Sinha, B.K., Sinhal, A., Verma, B.: A software measurement using artificial neural network and support vector machine. Int. J. Softw. Eng. Appl. 4(4) (2013)

    Google Scholar 

  10. Blei, D.M., Ng, A.Y., Jordan, M.I.: Latent Dirichlet allocation. J. Mach. Learn. Res. 3, 993–1022 (2003)

    MATH  Google Scholar 

  11. LeCun, Y.A., Bottou, L., Orr, G.B., Müller, K.-R.: Efficient backprop. In: Montavon, G., Orr, G.B., Müller, K.-R. (eds.) Neural Networks: Tricks of the Trade. LNCS, vol. 7700, pp. 9–48. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-35289-8_3

    Chapter  Google Scholar 

  12. Pai, S.: An operational performance model of breadth-first search (2017)

    Google Scholar 

  13. ISCAS89 Sequential Benchmark Circuits. http://www.pld.ttu.ee/maksim/benchmarks/iscas89/verilog. Accessed 01 Mar 2019

  14. Vivado Design Suite - HLx Editions. https://www.xilinx.com/products/design-tools/vivado.html. Accessed 01 Mar 2019

  15. Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, Hoboken (1999)

    Google Scholar 

  16. Cormen, T.H., Leiserson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms. The MIT Press, Cambridge (2001)

    MATH  Google Scholar 

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Correspondence to Priyanka Panigrahi , Rajesh Kumar Jha or Chandan Karfa .

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Panigrahi, P., Jha, R.K., Karfa, C. (2019). User Guided Register Manipulation in Digital Circuits. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_39

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  • DOI: https://doi.org/10.1007/978-981-32-9767-8_39

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