Abstract
This brief presents the design of 16-bit and 32-bit heterogeneous adders. For designing efficient adder architecture in terms of power, area and speed, a number of research works have been implemented to design an optimized architecture. This paper gives a comparative analysis of previously presented designs and the proposed heterogeneous adder architectures to validate a trade-off between power, area and delay. The proposed heterogeneous adder designs consist of cascading of ripple carry adder (RCA) and carry-lookahead adder (CLA) and are implemented in Xilinx Vivado 2017.1 design tool and FPGA-Kintex7 (xc7k70tfbv676-1) device without any constraints. These proposed adders are coded with VHDL language for obtaining better performance parameters in comparison with other reported adders for different application points of view.
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Mahapatro, S., Rout, S.S. (2020). FPGA Implementation of 16-Bit and 32-Bit Heterogeneous Adders. In: Pradhan, G., Morris, S., Nayak, N. (eds) Advances in Electrical Control and Signal Systems. Lecture Notes in Electrical Engineering, vol 665. Springer, Singapore. https://doi.org/10.1007/978-981-15-5262-5_35
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DOI: https://doi.org/10.1007/978-981-15-5262-5_35
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