Pipelined Implementation of Millar-Rabin Primality Tester Using Altera FPGA Kit

Abstract

Due to the demand for large prime numbers to be used by many public key cryptographic systems such as RSA and SSC (Schmidt-Samoa cryptosystem), this led for the development of fast and reliable methods for primality testing to determine whether a given integer is prime or composite. Many algorithms were proposed by to address the efficient method of testing the primality of the integer number. In this paper, we propose a pipelined reconfigurable FPGA implementation for the primality testing coprocessor using Millar-Rabin method by employing the maximum possible parallelism of the internal operations. The proposed design targeted the ${\text{ALTERA Cyclone }}\,{\text{IV FPGA}}$ (${\text{EP}}4{\text{CGX}}22{\text{CF}}19{\text{C}}7)$ along with ${\text{Quartus II}}$ simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed parallel architecture implementation has recorded: critical path delay of $22.65 \,{\text{ns}}$, maximum operational frequency of $51.11\,{\text{MHz}}$, hardware design area (number of logic elements) of $6184\,{\text{LEs}}$, and total thermal power dissipation estimated as 151.30 mW. Consequently, the proposed PT architecture can be efficiently employed by many public key cryptographic mechanisms.

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