High-Accurate, Area-Efficient Approximate Multiplier for Error-Tolerant Applications

Abstract

Due to increased applications of embedded systems, the need for fast and area-efficient components has become essential building blocks in the design phase. Most of the signal processing applications, image processing applications, are using efficient hardware blocks specific to the functionality in the name of error-tolerant blocks while compromising for minute error that may cause negligible deviation from the accurate result. The contemporary basic building blocks that needed for computation are greatly replaced by error-tolerant logic blocks due to the advantage of improvement in design optimization. In this paper, an error-tolerant multiplier is proposed with a new technique for accuracy improvement and area efficiency. The technique involved in this work is reframing the partial products to meet the multiplication product to the nearest accurate value. Simulation results for an 8 × 8 multiplier are observed and are comparable with greater improvement in the area at sustained delay characteristics. Observations are carried in Xilinx environment and achieved 57% of area improvement within the acceptable accuracy range from 55% to 100% than the existing error-tolerant design.