Abstract
The purpose of this work is to develop VLSI DSP architectures for CRC-32 generator polynomial equation to improve better throughput with less number of clock pulses. In this paper, IIR filter-based design method is proposed. Different levels of architectures are proposed to achieve the requirement. LFSR is used in developing VLSI DSP architectures. These architectures had been implemented in Xilinx tool.
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Campobello G, Patane G, Russo M (2003) Parallel CRC realization. IEEE Trans Comput 52(10):1312–1319
Zhang X, Parhi KK (2004) High-speed architectures for parallel long BCH encoders. In: Proceedings of the ACM great lakes symposium on VLSI, Boston, MA, Apr 2004, pp 1–6
Derby JH (2001) High speed CRC computation using state-space transformation. In: Proceedings of the global telecommunications conference 2001, GLOBECOM’01, vol 1, pp 166–170
Cheng C, Parhi KK (2009) High speed VLSI architecture for general linear feedback shift register (LFSR) structures. In: Proceedings of the 43rd Asilomar conference on signals, systems and computers, Monterey, CA, Nov 2009, pp 713–717
Jung J, Yoo H, Lee Y, Park I (2015) Efficient parallel architecture for linear feedback shift registers. IEEE Trans Circuits Syst II Express Briefs 62(11):1068–1072
Huo Y, Li X, Wang W, Liu D (2015) High performance table-based architecture for parallel CRC calculation. In: The 21st IEEE international workshop on local and metropolitan area networks, Beijing, pp 1–6
Ayinala M, Parhi KK (2011) High-speed parallel architectures for linear feedback shift registers. IEEE Trans Signal Process 59(9):4459–4469
Ayinala M, Parhi KK (2010) Efficient parallel VLSI architecture for linear feedback shift registers. In: IEEE workshop on SiPS, Oct 2010, pp 52–57
Varma RAC, Subbarao MV, Raju GRLVNS (2019) High throughput VLSI architectures for CRC-12 computation. In: Satapathy SC et al (eds) ICETE 2019. LAIS, vol 3. Springer Nature Switzerland AG 2020, pp 704–711
Varma RAC, Apparao YV (2018) High throughput VLSI architectures for CRC-16 computation in VLSI signal processing. In: Anguera J et al (eds) Microelectronics, electromagnetics and telecommunications. Lecture notes in electrical engineering, vol 471. Springer Nature Singapore Pte Ltd
Ayinala M, Brown MJ, Parhi KK (2012) Pipelined parallel FFT architectures via folding transformation. IEEE Trans VLSI Syst 20(6):1068–1081
Garrido M, Parhi KK, Grajal J (2009) A pipelined FFT architecture for real-valued signals. IEEE Trans Circuits Syst I Regul Pap 56(12):2634–2643
Cheng C, Parhi KK (2007) High-throughput VLSI architecture for FFT computation. IEEE Trans Circuits Syst II Express Briefs 54(10):863–867
Cheng C, Parhi KK (2008) Hardware-efficient low-latency architecture for high-throughput rate Viterbi decoders. IEEE Trans Circuits Syst II Express Briefs 55(12):1254–1258
Liu Y, Parhi KK (2016) Architectures for recursive digital filters using stochastic computing. IEEE Trans Signal Process 64(14):3705–3718
Prakash MS, Shaik RA (2013) Low-area and high-throughput architecture for an adaptive filter using distributed arithmetic. IEEE Trans Circuits Syst II 60(11):781–785
Dake JL, Terlapu SK (2016) Implementation of high-throughput digit-serial redundant basis multiplier over finite field. IOSR J VLSI Signal Process (IOSR-JVSP) 6(4):35–45. Ver. I, e-ISSN; 2319-4200, ISSN No.: 2319-4197
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Varma, R.A.C., Subbarao, M.V., Varma, D.R., Raju, G.R.L.V.N.S. (2021). High-Throughput VLSI Architectures for VLSI Signal Processing. In: Chowdary, P., Chakravarthy, V., Anguera, J., Satapathy, S., Bhateja, V. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 655. Springer, Singapore. https://doi.org/10.1007/978-981-15-3828-5_37
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DOI: https://doi.org/10.1007/978-981-15-3828-5_37
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