Abstract
Aiming at the problem of memory test power caused by the increasing proportion of embedded memory in multi-core SoC, this paper analyzes the existing issue and proposes a configurable MBIST controller to reduce test power consumption. This paper adopts MBIST configuration scan-chain to organize test groups and adopts a configurable PLL scan-chain to drive memories to its working frequency. Clock optimization method is also adopted to reduce test power. The method proposed has the advantages of low test power, flexible test configuration and less hardware added. The method can also diagnose the site of failing memories. The actual testing of the multi-core SoC on ATE V93000 shows that the proposed method effectively reduces power consumption, and meets the requirement of memory test.
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Hu, C., Li, X., Fu, Z., Tang, Q., Zhao, R. (2019). The Implementation of a Configurable MBIST Controller for Multi-core SoC. In: Xu, W., Xiao, L., Li, J., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2019. Communications in Computer and Information Science, vol 1146. Springer, Singapore. https://doi.org/10.1007/978-981-15-1850-8_8
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DOI: https://doi.org/10.1007/978-981-15-1850-8_8
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