Abstract
L3cache is an essential part of microchips, which is integrated into most of the microchips such as Intel and AMD chips. FeiTeng serial microchips is an independent research and designed microchip. Our research is based on a 64-cores multi-socket FeiTeng chip. To increase the performance of this chip, L3cache is designed for this chip. This paper first discusses the design of L3cache. Then two crucial evaluation indexes, the latency and bandwidth, are researched. From the simulation, it can be found that when opening L3cache, the latency can reduce 10% at most compared with the latency when closing L3cahce. Moreover, when opening L3cache, the bandwidth can increase twice under the circumstance of accessing a small amount of data. Considering the analysis, it can be concluded that for a multi-socket, multi-core system, L3cache can largely improve the systemic performance.
This work is supported by HGJ under Grant 2018ZX01029-103.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Mayfield, M.J., O’connell, F.P., Ray, D.S.: Cache prefetching of L2 and L3. Google Patents (2002)
Hwang, K., Jotwani, N.: Advanced Computer Architecture, Third edn. McGraw-Hill Education, New York City (2016)
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, Sixth edn, pp. 78–148. Morgan Kaufmann Publishers Inc., San Francisco (2017)
Chang, M.T.: Technology implications for large last-level caches. Dissertation, University of Maryland at College Park 2013 (2013)
Chang, M.T., Rosenfeld, P., Lu, S.-L., Jacob, B.: Technology comparison for large last-level caches (L3Cs): low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), pp. 143–154 (2013). https://doi.org/10.1109/hpca.2013.6522314
Ahn, H.K., Choi, S., Jung, S.: Evaluation of STT-MRAM L3 cache in 7 nm FinFET process’. In: 2018 International Conference on Electronics, Information, and Communication (ICEIC), pp. 1–4 (2018)
Schauer, B.: Multicore processors–a necessity, pp. 1–14. ProQuest discovery guides (2008)
Guo, X., Ipek, E., Soyata, T.: Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. SIGARCH Comput. Archit. News 38(3), 371–382 (2010). https://doi.org/10.1145/1816038.1816012
Sirhan, N.N., Serhan, I.S.: Multi-core processors: concepts and implementations. Int. J. Comput. Sci. Inf. Technol. 10(1), 1–10 (2018). https://doi.org/10.5121/ijcsit.2018.10101
Dropps, F.R., Anderson, M., Malewicki, M.: Packet tunneling for multi-node, multi-socket systems. Google Patents (2019)
Tsien, B., Broussard, B.P., Kalyanasundharam, V.: Multi-node system low power management. Google Patents (2019)
Deb, S., Ganguly, A., Pande, P.P., Belzer, B., Heo, D.: Wireless NoC as interconnection backbone for multicore chips: promises and challenges. IEEE J. Emerg. Sel. Top Circ. Syst. 2(2), 228–239 (2012). https://doi.org/10.1109/JETCAS.2012.2193835
Louri, A., Kodi, A.K.: An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs). IEEE Trans. Parallel Distrib. Syst. 15(12), 1093–1104 (2014). https://doi.org/10.1109/TPDS.2004.75
Sokolinsky, L.B.: Analytical estimation of the scalability of iterative numerical algorithms on distributed memory multiprocessors. Lobachevskii J. Math. 39(4), 571–575 (2018). https://doi.org/10.1134/S1995080218040121
Xie, M., Lu, Y.T., Wang, K.F., Liu, L., Cao, H.J., Yang, X.J.: Tianhe-1A interconnect and messagepassing services. IEEE Micro 32(1), 8–20 (2012). https://doi.org/10.1109/mm.2011.97
Liao, X.K., et al.: High performance interconnect network for Tianhe system. J. Comput. Sci. Technol. 30(2), 259–272 (2015). https://doi.org/10.1007/s11390-015-1520-7
Liao, X., Xiao, L., Yang, C., Lu, Y.: MilkyWay-2 supercomputer: system and application. Front. Comput. Sci. 8(3), 345–356 (2014). https://doi.org/10.1007/s11704-014-3501-3
Yang, X.J., Liao, X.K., Lu, K., Hu, Q.F., Song, J.Q., Su, J.S.: The TianHe-1A supercomputer: its hardware and software. J. Comput. Sci. Technol. 26(3), 344–351 (2011). https://doi.org/10.1007/s02011-011-1137-8
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Li, N., Deng, R., Zhang, Y., Zhou, H. (2019). Design Discussion and Performance Research of the Third-Level Cache in a Multi-socket, Multi-core Microchip. In: Xu, W., Xiao, L., Li, J., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2019. Communications in Computer and Information Science, vol 1146. Springer, Singapore. https://doi.org/10.1007/978-981-15-1850-8_10
Download citation
DOI: https://doi.org/10.1007/978-981-15-1850-8_10
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-1849-2
Online ISBN: 978-981-15-1850-8
eBook Packages: Computer ScienceComputer Science (R0)