Abstract
Computational requirements of Artificial Neural Networks (ANNs) are so vastly different from the conventional architectures that exploring new computing paradigms, hardware architectures, and their optimization has gained momentum. ANNs use large number of parallel operations because of which their implementation on conventional computer hardware becomes inefficient. This paper presents a new design methodology for Multi-operand adders. These adders require multi-bit carries which makes their design unique. Theoretical upper bound on the size of sum and carry in a multi-operand addition for any base and any number of operands is presented in this paper. This result is used to design modular 4-operand, 4-bit adder. This module computes the partial sums using a look-up-table. These modules can be connected in a hierarchical structure to implement larger adders. Method to build a 16 bit 16 operand adder using this basic 4-bit 4-operand adder block is presented. Verilog simulation results are presented for both 4 × 4 and 16 × 16 adders. Design strategy used for the 16 × 16 adder may further be extended to more number of bits or operands with ease, using the guidelines discussed in the paper.
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The authors would like to thank C-Quad Research, Belagavi for all the support.
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Mayannavar, S., Wali, U. (2019). Design of Hardware Accelerator for Artificial Neural Networks Using Multi-operand Adder. In: Gani, A., Das, P., Kharb, L., Chahal, D. (eds) Information, Communication and Computing Technology. ICICCT 2019. Communications in Computer and Information Science, vol 1025. Springer, Singapore. https://doi.org/10.1007/978-981-15-1384-8_14
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DOI: https://doi.org/10.1007/978-981-15-1384-8_14
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