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Ferroelectric-Gate Field Effect Transistor Memories pp 125–145Cite as

ZnO/Pb(Zr,Ti)O3 Gate Structure Ferroelectric FETs

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Part of the book series: Topics in Applied Physics ((TAP,volume 131))

Abstract

We have developed a ferroelectric-gate field-effect transistor (FeFET) composed of heteroepitaxially stacked oxide materials. A semiconductor film of ZnO, a ferroelectric film of Pb(Zr,Ti)O3 (PZT), and a bottom-gate electrode of SrRuO3 (SRO) are grown on a SrTiO3 substrate. Structural characterization shows a heteroepitaxy of the fabricated ZnO/PZT/SRO/STO structure with a good crystalline quality and absence of an interface reaction layer. When gate voltages applied to the bottom electrode are swept between −10 V and +10 V, the ON/OFF ratio of drain currents is higher than 105. Such a high ratio is preserved even after 3.5 months; the extrapolation of retention behavior predicts a definite memory window over 10 years. We also switched FeFET channel conductance by applying short pulses to a gate electrode and found that the switching of the FeFET is due to domain wall motion in a ferroelectric film. Polarization reversal starts from a region located under source and drain electrodes and travels along the direction of channel length. In addition, domain wall velocity increases as the domain wall gets closer to the source and drain electrodes in the ferroelectric film. Therefore, the FeFET has the merit of high operation speeds at scale. Then, we demonstrate a 60-nm-channel-length FeFET. The drain current ON/OFF ratio was about three orders of magnitude for write pulse widths as narrow as 10 ns. Although the channel length is set at 60 nm, the conductance can be varied continuously by varying the write pulse width.

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Acknowledgements

We would like to thank Yu Nishitani, Hiroyuki Tanaka, Michihito Ueda, Atsushi Omote, Ayumu Tsujimura, Eiji Fujii, Yoshihisa Kato, Yasuhiro Shimada, Daisuke Ueda, and Eisuke Tokumitsu for valuable discussions and excellent experimental assistance.

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Authors and Affiliations

  1. Advanced Research Division, Panasonic Corporation, 3-4 Hikaridai, Seika-cho, Soraku-gun, Kyoto, 619-0237, Japan

    Yukihiro Kaneko

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  1. Yukihiro Kaneko
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Correspondence to Yukihiro Kaneko .

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Editors and Affiliations

  1. School of Electrical and Computer Engineering, University of Seoul, Seoul, Korea (Republic of)

    Byung-Eun Park

  2. Frontier Collaborative Research Center, Tokyo Institute of Technology, Yokohama, Japan

    Hiroshi Ishiwara

  3. Graduate School of Engineering Science, Osaka University, Osaka, Japan

    Masanori Okuyama

  4. National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan

    Shigeki Sakai

  5. Advanced Materials Engineering for Information and Electronics, Kyunghee University, Yongin, Korea (Republic of)

    Sung-Min Yoon

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Kaneko, Y. (2020). ZnO/Pb(Zr,Ti)O3 Gate Structure Ferroelectric FETs. In: Park, BE., Ishiwara, H., Okuyama, M., Sakai, S., Yoon, SM. (eds) Ferroelectric-Gate Field Effect Transistor Memories. Topics in Applied Physics, vol 131. Springer, Singapore. https://doi.org/10.1007/978-981-15-1212-4_7

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