Abstract
In this chapter, recent topics on oxide-channel ferroelectric-gate transistors were presented. First, nonvolatile memory circuit application of ferroelectric-gate transistors is discussed by comparing it with Flash memory. It is pointed out that “read disturb” may become serious in the memory circuits using ferroelectric-gate transistors in contrast to Flash memory. To solve the read disturb problem, two-transistor memory cell structures are presented for both NAND and NOR configurations. In NAND configuration, one memory cell consists of parallel connection of a memory transistor and a pass transistor, whereas one memory cell consists of series connection of a memory transistor and a cut-off transistor in NOR configuration. Next, two-transistor cell NAND memory arrays using oxide-channel ferroelectric-gate transistors for both memory and pass transistors have been fabricated. It is confirmed that the stored “off” data in unselected cells remain almost intact during the readout procedures of a selected cell. Next, solution process is demonstrated to fabricate oxide-channel ferroelectric-gate transistors. All-oxide, all-solution-processed ferroelectric-gate transistors are demonstrated. In addition, newly developed nano-rheology printing (n-RP) technology, which utilizes direct nanoimprint of oxide gel films, is used to fabricate oxide-channel ferroelectric thin-film transistors without using conventional lithography process.
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Acknowledgements
The author would like to acknowledge members of JST ERATO, “Shimoda Nano-Liquid Process” project.
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Tokumitsu, E., Shimoda, T. (2020). Applications of Oxide-Channel Ferroelectric-Gate Thin-Film Transistors. In: Park, BE., Ishiwara, H., Okuyama, M., Sakai, S., Yoon, SM. (eds) Ferroelectric-Gate Field Effect Transistor Memories. Topics in Applied Physics, vol 131. Springer, Singapore. https://doi.org/10.1007/978-981-15-1212-4_21
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DOI: https://doi.org/10.1007/978-981-15-1212-4_21
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