Abstract
Band-to-band tunneling at the source–channel junction of multigate tunnel field effect transistors (TFETs) plays a major role to boost ON current for eliminating short channel effects (SCE). In this paper, the conventional double gate TFET structure (DG-TFET) is designed and modified by applying gate engineering to design triple gate TFET (TG-TFET). The work mainly focuses on drain current (ION) assessment, fast switching ratio (ION/IOFF), and subthreshold swing (SS) by comparing between conventional DG-TFET and proposed TG-TFET with pocket intrinsic layers. The variation of drain current for different pocket intrinsic doping conditions on TFET performance has been reviewed and demonstrated with SILVACO TCAD simulator. The pocket intrinsic triple gate TFET shows a higher ION and better ION/IOFF ratio of 5.51 for source and pocket doping of 1 ×1020 cm−3 and 1 × 1015 cm−3. This provides 68.51% fast switching ratio as compared to other non-conventional tunnel FETs. But the subthreshold swing (SS) is limited by variation of pocket doping from 100 to 1018 cm−3 for TG-PI-TFET, since DG-PI-TFET provides better subthreshold swing of 23.93 mV/dec (≪60 mV/dec) considering the leakage current for low-power applications.
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References
Thomas, N., Philip Wong, H.S.: The end of Moore’s law: a new beginning for information technology. IEEE J. Comput. Sci. Eng. 19(2), 41–50 (2017)
Nikonov, D.E., Young, I.A.: Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proc. IEEE 101(12), 2498–2533 (2013)
Seabaugh,. A., Alessandri, C., Min Li, H., Paletti, P.: Steep slope transistors: tunnel FETs and beyond,.In: Proceedings of 46th European Solid State Device Research Conference, pp. 349–351. IEEE (2016)
Choi, W.Y., Park, B.G., Lee, J.D., King Liu, T.J.: Tunneling field-effect transistors (TFETs) with sub-threshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)
Zhang, Q., Zhao, W., Seabaugh, A.: Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27(4), 297–300 (2006)
Hraziia, Vladimirescu, A., Amara, A., Anghel, C.: An Analysis on the Ambipolar Current in Si Double-Gate Tunnel FETs, Solid-State Electronics, vol. 70, pp. 67–72. Elsevier (2012)
Bagga, N., Sarkhel, S., Sarkar, S.K.: Recent research trends in gate engineered tunnel FET for improved current behavior by subduing the ambipolar effects: a review. In: Proceedings of IEEE International Conference on Computing, Communication and Automation. India (2015)
Pal, A., Sachid, A.B., Gossner, H., Rao, V.R.: Insights Into the design and optimization of tunnel-FET devices and circuits. IEEE Trans. Electron Devices 58(4), 1045–1053 (2011)
Datta, S., Liu, H., Narayanan, V.: Tunnel FET Technology: A Reliability Perspective, Microelectronics Reliability, vol. 54, pp. 861–874. Elsevier (2014)
Leonelli, D., Vandooren, A., Rooyackers, R., Gendt, S., Heyns, M.M., Groeseneken, G.: Drive Current Enhancement in p-Tunnel FETs by Optimization of the Process Conditions, Solid-State Electronics, vol. 65, pp. 28–32. Elsevier (2011)
Boucart, K., Ionescu, A.M.: Length Scaling of the Double Gate Tunnel FET with a High-K Gate Dielectric, Solid-State Electronics, vol. 51, pp. 1500–1507. Elsevier (2007)
Verhulst, A.S., Sorée, B., Leonelli, D., Vandenberghe, W.G., Groeseneken, G.: Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J. Appl. Phys. 107(2), 024518 (2010)
Seunggyu, J.,Hyungtak, K., Hwan, C.: Characteristics of recess structure tunneling field effect transistor for high on current drivability. J. Semicond. Technol. Sci. 18(3) (2018)
Wei, S., Zhang, G., Geng, L., Shao, Z., Yang, C.F.: Comparison of the Performance Improvement for the Twonovel SOI-Tunnel FETs with the Lateral Dual-Gate and Triple-Gate, Microsystem Technologies. Springer, Berlin (2018)
Jhaveri, R., Nagavarapu, V., Woo, J.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58(1), 80–86 (2011)
Kumar, M.J., Ramaswamy, S.: Double gate symmetric tunnel FET: investigation and analysis. IET Circuits Devices Syst. 11(4), 365–370 (2017)
Graef, M., Hosenfeld, F., Horst, F., Farokhnejad, A., Hain, F., Iñíguez, B., Kloes, A.: Advanced Analytical Modeling of Double-Gate Tunnel-FETs—A Performance Evaluation, Solid-State Electronics, vol. 141, pp. 31–39. Elsevier (2018)
Gracia, D., Nirmal, D.: Performance Analysis of Dual Metal Double Gate Tunnel-FETs for Ultralow Power Applications, Nanoelectronic Materials and Devices–LNEE, vol. 466, pp. 11–18. Springer, Berlin (2018)
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Dutta, R., Paitya, N. (2020). Effect of Pocket Intrinsic Doping on Double and Triple Gate Tunnel Field Effect Transistors. In: Kundu, S., Acharya, U.S., De, C.K., Mukherjee, S. (eds) Proceedings of the 2nd International Conference on Communication, Devices and Computing. ICCDC 2019. Lecture Notes in Electrical Engineering, vol 602. Springer, Singapore. https://doi.org/10.1007/978-981-15-0829-5_25
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DOI: https://doi.org/10.1007/978-981-15-0829-5_25
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