Abstract
Hardware security is becoming increasingly critical in SoC designs. A SoC integrates several modules to form a larger system. To reduce the time-to-market and design efforts, reusable, pretested modules called intellectual properties (IPs) are incorporated in the design. Hence, designing mainly relies on interconnection of modules that may lead to unintentional functional paths. As SoC may contain several secure and non-secure modules, data propagation in the design must be carefully analyzed. There exist various forms of security attacks like tampering, repudiation and privilege elevation. These attacks may affect system manufacturers, system designers or the end users. A designer invests a lot on design in terms of both money and time, and SoC protection becomes highly important. Security Path Verification (SPV) App of JasperGold Tool by Cadence is used to check the sanctity of the data in the design. SPV uses formal techniques to verify the data propagation in the design.
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Asha, K.S., Mendonca, O.S., Bhandarkar, R., Srinivas, R. (2020). Data Flow Verification in SoC Using Formal Techniques. In: Kalya, S., Kulkarni, M., Shivaprakasha, K. (eds) Advances in Communication, Signal Processing, VLSI, and Embedded Systems. Lecture Notes in Electrical Engineering, vol 614. Springer, Singapore. https://doi.org/10.1007/978-981-15-0626-0_2
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DOI: https://doi.org/10.1007/978-981-15-0626-0_2
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