Abstract
The increased usage of image and video compression in real-time applications has led to pressing need for efficient compression algorithms and dedicated hardware circuits. The aim of this proposed paper is to design an efficient adder compressor for approximated two-dimensional discrete cosine transform realization. This paper deals with enhancing the existing XOR-based adder compressor to a better XOR-XNOR-based architecture. The proposed compressors offer less delay, low power with the penalty of area. The proposed method provides less power consumption and offers high speed as compared to conventional design by 11.5% and 2%, respectively.
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Lahoti, R.R., Agarwal, S., Balamurugan, S., Marimuthu, R. (2020). Realization of 2-D DCT Using Adder Compressor. In: Das, K., Bansal, J., Deep, K., Nagar, A., Pathipooranam, P., Naidu, R. (eds) Soft Computing for Problem Solving. Advances in Intelligent Systems and Computing, vol 1057. Springer, Singapore. https://doi.org/10.1007/978-981-15-0184-5_49
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DOI: https://doi.org/10.1007/978-981-15-0184-5_49
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