Abstract
Digital FIR filters have been used for various signal processing tasks in embedded systems. This paper presents a novel architecture for implementation of an FIR differentiator in FPGA designed for a specific application. The designed component is to estimate the velocity from the suspension displacement in a semi-active suspension controller. The architectures of FIR are modified based on the direct and transposed form, with incremental changes in the manner in which the constant-coefficient multiplication is executed. The recoding of constant FIR filter coefficients using Canonic Signed Digit representation is explored. Three architectures are designed and compared for efficient usage of area of implementation in FPGA. It is observed that the architecture using CSD requires 16% lesser area, and the optimized architecture is an additional 5% more area-efficient and \(16\%\) lesser in complexity of design because of sharing of resources. An overall reduction in power consumption by \(3\%\) is observed and the computation of the FIR filter convolution sum is faster by \(17\%\).
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Chen MC, Chen TT (2014) Minimizing design costs of an FIR filter using a novel coefficient optimization algorithm. Math Probl Eng 1–9. https://doi.org/10.1155/2014/497471
Duraiswamy P, Bauwelinck J, Vandewege J (2011) Efficient implementation of 90 phase shifter in FPGA. EURASIP J Adv Sig Proc 2011(1):32
Eligar S, Banakar RM (2014) A model based approach for design of semiactive suspension using variable structure control. Int J Tech Res Appl. e-ISSN 2320–8163
Eligar S, Banakar RM (2018) Optimization of control algorithm for semi-active suspension system. In: 2018 proceedings of the international conference on intelligent computing and sustainable system
Illa A, Haridas N, Elias E (2016) Design of multiplier-less FIR filters with simultaneously variable bandwidth and fractional delay. Eng Sci Tech Int J 19(3):1160–1165
Mitra SK, Kaiser JF (1993) Handbook for digital signal processing. Wiley, New York
Parhi KK (2007) VLSI digital signal processing systems: design and implementation. Wiley, New York
Proakis JG (2001) Digital signal processing: principles algorithms and applications. Pearson Education, India
Thong J, Nicolici N (2010) A novel optimal single constant multiplication algorithm. In: Proceedings of the 47th design automation conference, pp 613–616. ACM
Thong J, Nicolici N (2011) An optimal and practical approach to single constant multiplication. IEEE Trans Comput-Aided Des Integr Circ Syst 30(9):1373–1386
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Eligar, S., Banakar, R.M. (2020). Area and Power Efficient Multiplier-Less Architecture for FIR Differentiator. In: Ranganathan, G., Chen, J., Rocha, Á. (eds) Inventive Communication and Computational Technologies. Lecture Notes in Networks and Systems, vol 89. Springer, Singapore. https://doi.org/10.1007/978-981-15-0146-3_47
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DOI: https://doi.org/10.1007/978-981-15-0146-3_47
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