Power and Delay Comparison of 7:3 Compressor Designs Based on Different Architectures of XOR Gate

Abstract

This paper presents the power and delay comparison of 7:3 compressor circuit designed using three different architectures of XOR gate which are based upon mirror circuit, 4-transistor, (4-T) and transmission gate (TG). The compressors have been implemented in transistor level at 180 nm technology and the functionality is verified in Cadence-spectre. Among the 7:3 compressors, the design utilizing the TG-based XOR gate is exhibiting least power consumption and the least delay is exhibited by the design which is based upon mirror circuit-based XOR gate.

Appendix

The Karnaugh map for the output $q_{b1}$ is shown below:

Considering the circled minterms:

$$ \begin{aligned} q_{b1} & = \left[ {x_{4} x_{3} + x_{5} x_{3} + x_{5} x_{4} + x_{5} x_{4} x_{3} + x_{6} x_{3} + x_{6} x_{4} + x_{6} x_{4} x_{3} + x_{6} x_{5} + x_{6} x_{5} x_{3} + x_{6} x_{5} x_{4} } \right]\overline{{q_{b2} }} \\ & = \left[ {x_{4} x_{3} + x_{5} x_{3} + x_{5} x_{4} \left( {1 + x_{3} } \right) + x_{6} x_{3} + x_{6} x_{4} \left( {1 + x_{3} } \right) + x_{6} x_{5} \left( {1 + x_{3} + x_{4} } \right)} \right]\overline{{q_{b2} }} \\ & = \left[ {x_{4} x_{3} + x_{5} x_{3} + x_{5} x_{4} + x_{6} x_{3} + x_{6} x_{4} + x_{6} x_{5} } \right]\overline{{q_{b2} }} \\ & = \left[ {x_{6} x_{5} + x_{4} x_{3} + x_{5} \left( {x_{3} + x_{4} } \right) + x_{6} \left( {x_{3} + x_{4} } \right)} \right]\overline{{q_{b2} }} \\ & = \left[ {x_{6} x_{5} + x_{4} x_{3} + x_{5} \left( {x_{3} + x_{4} } \right) + x_{6} \left( {x_{3} + x_{4} } \right)} \right]\overline{{q_{b2} }} \\ \end{aligned} $$

(8)

$$ q_{b1} = \left[ {x_{6} x_{5} + x_{4} x_{3} + \left( {x_{3} + x_{4} } \right)\left( {x_{5} + x_{6} } \right)} \right]\overline{{q_{b2} }} $$

(9)