Abstract
Gaussian noise often appears in images, and in order to enhance the image quality, it is necessary to use a gaussian filter to preprocess the acquired image. The gaussian filter hardware accelerator module is designed through algorithm pipeline design and HLS instruction optimization by the HLS developed by Xilinx. At last, we analyze the image processing speed and resource occupancy on different hardware platforms. Experimental results show that the gaussian filter based on FPGAs is much faster than that on CPUs, and reduces the difficulty of porting the algorithm on different hardware platforms, which greatly shortens the development cycle of the project.
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Tian, Z., Liu, Z., Wang, S., Chen, D. (2019). Design and Implementation of Hardware Accelerator for Gaussian Filter Based on HLS. In: Wang, Y., Huang, Q., Peng, Y. (eds) Image and Graphics Technologies and Applications. IGTA 2019. Communications in Computer and Information Science, vol 1043. Springer, Singapore. https://doi.org/10.1007/978-981-13-9917-6_16
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DOI: https://doi.org/10.1007/978-981-13-9917-6_16
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