Abstract
This paper presents a novel asynchronous instruction cache suitable for self-timed system. The DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75 KB CAM for 8 KB instruction memory. We designed and simulated the proposed asynchronous cache including content addressable memory.
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Battogtokh, J. (2020). Implementation of Asynchronous Cache Memory. In: Pan, JS., Li, J., Tsai, PW., Jain, L. (eds) Advances in Intelligent Information Hiding and Multimedia Signal Processing. Smart Innovation, Systems and Technologies, vol 156. Springer, Singapore. https://doi.org/10.1007/978-981-13-9714-1_45
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DOI: https://doi.org/10.1007/978-981-13-9714-1_45
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