Abstract
In this paper, a verification testbench-based UVM is established for a CAN IP. To adapt to some features of the CAN IP and improve the efficiency of the verification, appropriate strategies and methods are implemented, such as the constraint random stimulus, register model with indirect indexed registers, the coverage-driven strategy, and a reference model for automatic comparison. It’s proved that UVM-based verification testbench can make the process of verification clearer and more efficient. During the verification, we find some problems of the CAN IP. After solving them, we take regression test and all these problems are solved. Finally, we collect the function coverage and code coverage as the evaluation of the verification, and two of them could prove that the CAN IP could be used for FPGA firmware design.
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Han, J., Fu, P., Qiao, J. (2020). UVM-Based CAN IP Verification. In: Pan, JS., Li, J., Tsai, PW., Jain, L. (eds) Advances in Intelligent Information Hiding and Multimedia Signal Processing. Smart Innovation, Systems and Technologies, vol 156. Springer, Singapore. https://doi.org/10.1007/978-981-13-9714-1_13
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DOI: https://doi.org/10.1007/978-981-13-9714-1_13
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Online ISBN: 978-981-13-9714-1
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