Abstract
Cache memory plays an important role in the efficient execution of today’s big data-based applications. The high-performance computer has multicore processors to support parallel execution of different applications and threads. These multicore processors are placed in a single chip called chip multiprocessor (CMP). Each core has its own private cache memories, and all the core share a common last-level cache (LLC). The performance of LLC plays a major role in handling big data-based applications. In this paper, we have done a survey on the innovative techniques proposed for efficiently handling big data-based applications in the LLC of CMPs.
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References
R. Balasubramonian, N.P. Jouppi, N. Muralimanohar, Multi-Core Cache Hierarchies (Morgan and Claypool Publishers, 2011)
G.H. Loh, 3D-stacked memory architectures for multi-core processors. ACM SIGARCH Computer Architecture News 36, 453–464 (2008)
J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, S.W. Keckler, A NUCA substrate for flexible CMP cache sharing, in Proceedings of the 19th Annual International Conference on Supercomputing (ICS) (2005), pp. 31–40
U. Nawathe, M. Hassan, L. Warriner, K. Yen, B. Upputuri, D. Greenhill, A. Kumar, H. Park, An 8-Core 64-thread 64B power-efficient SPARC SoC, in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) (2007), pp. 108–590
AMD Athlon 64 X2 Dual-Core Processor for Desktop. (Online). Available: http://www.amd.com/us-en/Processors/ProductInformation/0,,30118948513041,00.html
J. Chang, G.S. Sohi, Cooperative caching for chip multiprocessors, in Proceedings of the International Symposium on Computer Architecture (ISCA) (2006), pp. 264–276
S. Das, H.K. Kapoor, Dynamic associativity management using fellow sets, in Proceedings of the 2013 International Symposium on Electronic System Design (ISED) (2013), pp. 133–137
M.K. Qureshi, D. Thompson, Y.N. Patt, The V-way cache: demand based associativity via global replacement. ACM SIGARCH Comput Archit. News 33(2), 544–555 (2005)
S. Das, H.K. Kapoor, Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsyst. 38(4), 263–275 (2014)
S. Das, H.K. Kapoor, Exploration of migration and replacement policies for dynamic NUCA over tiled CMPs, in Proceedings of the 28th International Conference on VLSI Design (VLSID) (2015)
C. Kim, D. Burger, S.W. Keckler, An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. ACM SIGOPS Operating Syst. Rev. 36, 211–222 (2002)
Z. Chishti, M.D. Powell, T.N. Vijaykumar, Distance associativity for high-performance energy-efficient non-uniform cache architectures, in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2003), pp. 55–66
J. Lira, C. Molina, A. Gonzalez, HK-NUCA: boosting data searches in dynamic non-uniform cache architectures for chip multiprocessors, in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing (IPDPS), (2011), pp. 419–430
W. Ding, M. Kandemir, Improving last level cache locality by integrating loop and data transformations, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2012), pp. 65–72
J.L. Hennessy, D.A. Patterson, Computer Architecture: A Quantitative Approach, 4th edn. (Elsevier, 2007)
A. El-Moursy, F. Sibai, V-set cache design for LLC of multi-core processors, in Proceedings of the IEEE 14th International Conference on High Performance Computing and Communication and IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS) (2012), pp. 995–1000
G.H. Loh, Y. Xie, B. Black, Processor design in 3D die-stacking technologies. IEEE Micro 27(3), 31–48 (2007)
Intel. Quad-Core Intel Xeon Processor 5400 Series, apr 2008. (Online). Available: http://download.intel.com/design/xeon/datashts/318589.pdf
D. Rolán, B.B. Fraguela, R. Doallo, Adaptive line placement with the set balancing cache, in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2009), pp. 529–540
S. Das, N. Polavarapu, P.D. Halwe, H.K. Kapoor, Random-LRU: a replacement policy for chip multiprocessors, in Proceedings of the International Symposium on VLSI Design and Test (VDAT) (2013)
D. Sanchez, C. Kozyrakis, The ZCache: decoupling ways and associativity, in Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2010), pp. 187–198
P. Foglia, M. Comparetti, A workload independent energy reduction strategy for D-NUCA caches. J. Supercomput. 68, 157–182 (2013)
H. Kapoor, S. Das, S. Chakraborty, Static energy reduction by performance linked cache capacity management in Tiled CMPs, in Proceedings of the 30th ACM/SIGAPP Symposium On Applied Computing (SAC) (2015)
B.M. Beckmann, D.A. Wood, Managing wire delay in large chip-multiprocessor caches, in Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2004), pp. 319–330
B.M. Beckmann, D.A. Wood, TLC: transmission line caches, in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2003), pp. 43–54
Z. Chishti, M.D. Powell, T.N. Vijaykumar, Optimizing replication, communication, and capacity allocation in CMPs. ACM SIGARCH Comput. Archit. News 33, 357–368 (2005)
M. Zhang, K. Asanovic, Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors, Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA), vol. 0, (2005), , pp. 336–345
M. Hammoud, S. Cho, R. Melhem, Dynamic cache clustering for chip multiprocessors, in Proceedings of the 23rd International Conference on Supercomputing (ICS) (2009), pp. 56–67
D. Zhan, H. Jiang, S.C. Seth, STEM: spatiotemporal management of capacity for intra-core last level caches, in Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2010), pp. 163–174
M.K. Qureshi, A. Jaleel, Y.N. Patt, S.C. Steely, J. Emer, Adaptive insertion policies for high performance caching. ACM SIGARCH Comput. Archit. News 35(2), 381–391 (2007)
S.M. Khan, D.A. Jiménez, D. Burger, B. Falsafi, Using dead blocks as a virtual victim cache, in Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2010), pp. 489–500
R. Balasubramonian, J. Chang, T. Manning, J.H. Moreno, R. Murphy, R. Nair, S. Swanson, Near-data processing: Insights from a micro-46 workshop. IEEE Micro 34(4), 36–42 (2014)
H. Asghari-Moghaddam, A. Farmahini-Farahani, K. Morrow, J.H. Ahn, N.S. Kim, Near-DRAM acceleration with single-ISA heterogeneous processing in standard memory Mmodules. IEEE Micro 36(1), 24–34 (2016)
D. Park, J. Wang, Y.S. Kee, In-storage computing for Hadoop MapReduce framework: challenges and possibilities. IEEE Trans. Comput. 99, 1–1 (2016)
S.H. Pugsley, A. Deb, R. Balasubramonian, F. Li, Fixed-function hardware sorting accelerators for near data MapReduce execution, in Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD) (2015), pp. 439–442
B. Gu, A.S. Yoon, D.H. Bae, I. Jo, J. Lee, J. Yoon, J.U. Kang, M. Kwon, C. Yoon, S. Cho, J. Jeong, D. Chang, Biscuit: a framework for near-data processing of big data workloads, in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (2016), pp. 153–165
M. Gao, C. Kozyrakis, HRL: efficient and flexible reconfigurable logic for near-data processing, in Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA) (2016), pp. 126–137
V.T. Lee, A. Mazumdar, C.C.d. Mundo, A. Alaghi, L. Ceze, M. Oskin, POSTER: application-driven near-data processing for similarity search, in 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2017), pp. 132–133
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Das, P. (2020). Cache Memory Architectures for Handling Big Data Applications: A Survey. In: Elçi, A., Sa, P., Modi, C., Olague, G., Sahoo, M., Bakshi, S. (eds) Smart Computing Paradigms: New Progresses and Challenges. Advances in Intelligent Systems and Computing, vol 767. Springer, Singapore. https://doi.org/10.1007/978-981-13-9680-9_18
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DOI: https://doi.org/10.1007/978-981-13-9680-9_18
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