Skip to main content

Comparisons in L32 2k-Factorial and L25 Taguchi for the 16 nm FinFET Statistical Optimization Applications

  • Conference paper
  • First Online:
Intelligent Manufacturing and Mechatronics (SympoSIMM 2019)

Abstract

This project examines and analyzes the process parameter variance towards on-state drive current (ION) and leakage current (IOFF) towards the 16 nm double-gate FinFET (DG-FinFET) device by the implementation of 2k-factorial design, with comparisons made against an L25 Taguchi statistical method. Alterations with two levels for six process parameters consisting of the threshold voltage (VTH) doping dose, VTH doping tilt, polysilicon doping dose, polysilicon doping tilt, Source and Drain (S/D) doping dose and S/D doping tilt will be done to analyze and improve the results of both ION and IOFF. The physical characteristics of the device will be defined on the ATHENA module, with the ATLAS module then used to characterize its electrical properties. Consideration is made with the responses from both modules by the assistance of the L32 2k-factorial design to reduce the device’s variability as well as maximizing the value of ION while minimizing the IOFF value. By achieving both values, the ION/IOFF ratio are able to be maximized in order to reduce the power consumption of the device subsequently. The most dominant factor towards both ION and IOFF values is identified with polysilicon doping tilt, showcasing the largest standardized effects at the end of this experiment. The optimum values achieved with 2k-factorial design with ION and IOFF at 1648.48 μA/μm and 42.096 pA/μm respectively while achieving better ION/IOFF ratio with 39.160 × 106 as its ION have surpassed the value of ION achieved in Taguchi method that was valued at 1559.96 μA/μm. Importantly, the results acquired have met the predictions of the International Technology Roadmap Semiconductor (ITRS) 2013 for the year 2020.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Bhattacharya, D., Jha, N.K.: FinFETs: from devices to architectures. Adv. Electron. 2014, 1–21 (2014). https://doi.org/10.1155/2014/365689

    Article  Google Scholar 

  2. Mallik, A., Ryckaert, J., Mercha, A., Verkest, D., Ronse, K., Thean, A.: Maintaining Moore’s law: enabling cost-friendly dimensional scaling. In: Proceedings of the SPIE 9422, Extreme Ultraviolet (EUV) Lithography VI, 94221N (2015)

    Google Scholar 

  3. Vidya, S., Khan, A., Kamat, S.V., Venkritesh, V.: 3D FinFET for next generation nano devices. In: 2018 International Conference on Current Trends Towards Converging Technologies (ICCTCT) (2018). https://doi.org/10.1109/icctct.2018.8550967

  4. Kwon, D., Chatterjee, K., Tan, A.J., Yadav, A.K., Zhou, H., Sachid, A.B., Salahuddin, S.: Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors. IEEE Electron Device Lett. 39(2), 300–303 (2018)

    Article  Google Scholar 

  5. Gill, A., Madhu, C., Kaur, P.: Investigation of short channel effects in bulk MOSFET and SOI FinFET at 20 nm node technology. In: 2015 Annual IEEE India Conference (INDICON) (2015). https://doi.org/10.1109/indicon.2015.7443263

  6. Wang, M.C., Rao, Z.Y., Liu, H.Y., Tuan, F.Y., Liao, W.S., Lan, W.H.: DIBL effect gauging the integrity of nano-node n-channel FinFETs. In: 2017 6th International Symposium on Next Generation Electronics (ISNE) (2017). https://doi.org/10.1109/isne.2017.7968704

  7. Saxena, S., Member, S., Hess, C., Karbasi, H., Rossoni, A., Tonello, S., Mcnamara, P., Lucherini, S., Minehane, S., Dolainski, C., Quarantelli, M.: Variation in transistor performance and leakage in nano-scale technologies. IEEE Trans. Electron Devices 55, 131–144 (2008)

    Article  Google Scholar 

  8. Chang, R.D., Lin, P.H.: Simulation study of implantation angle variation and its impact on device performance. In: 2016 21st International Conference on Ion Implantation Technology (IIT) (2016). https://doi.org/10.1109/iit.2016.7882906

  9. Elgomati, H.A., Majlis, Burhanuddin Yeop, Ahmad, I., Salehuddin, F., Hamid, F.A., Zaharim, Azami, Mohamad, T.Z., Apte, P.R.: Statistical Optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage. Int. J. Phys. Sci. 6, 2372–2379 (2011)

    Google Scholar 

  10. Mah, S.K., Ahmad, I., Ker, P.J., Tan, K.P., Faizah, Z.A.N.: Modeling, simulation and optimization of 14 nm high-K/metal gate NMOS with Taguchi method. In: 2018 IEEE International Conference on Semiconductor Electronics (ICSE) (2018). https://doi.org/10.1109/smelec.2018.8481293

  11. Noor Faizah, Z.A., Ahmad, I., Ker, P.J., Menon, P.S., Afifah Maheran, A.H.: VTH and ILEAK optimization using Taguchi method at 32 nm bilayer graphene PMOS. J. Telecommun. Electron. Comput. Eng. 9, 105–109 (2017)

    Google Scholar 

  12. Othman, N.A.F., Azhari, F.N.N., Wan Muhamad Hatta, S.F., Soin, N.: Optimization of 7 nm strained germanium FinFET design parameters using Taguchi method and Pareto analysis of variance. ECS J. Solid State Sci. Technol. 7(4), 161–169 (2018)

    Article  Google Scholar 

  13. Goncalves, F., Duarte, C., Alves, P.: Development of an evaluation platform for statistical characterization of MOSFET model parameters. UPorto J. Eng. 3(1), 39–49 (2017). https://doi.org/10.24840/2183-6493_003.001_0004

    Article  Google Scholar 

  14. Saha, R., Bhowmick, B., Baishya, S.: Statistical dependence of gate metal work function on various electrical parameters for an n-channel Si step-FinFET. IEEE Trans. Electron Devices 64(3), 969–976 (2017). https://doi.org/10.1109/ted.2017.2657233

    Article  Google Scholar 

  15. Mei, S., Raghavan, N., Bosman, M., Pey, K.L.: Stochastic modeling of FinFET degradation based on a resistor network embedded metropolis Monte Carlo method. IEEE Trans. Electron Devices 65, 440–447 (2018). https://doi.org/10.1109/ted.2017.2785041

    Article  Google Scholar 

  16. Salehuddin, F., Zain, A.S.M., Idris, N.M., Yamin, A.K.M., Hamid, A.M.A., Ahmad, I., Menon, P.S.: Analysis of threshold voltage variance in 45 nm N-channel device using L27 orthogonal array method. Adv. Mater. Res. 903, 297–302 (2014)

    Article  Google Scholar 

  17. Kaharudin, K.E., Salehuddin, F., Zain, A.S.M., Aziz, M.N.I.A.: Taguchi modelling with the interaction test for higher drive current in WSIx/TIO2 channel vertical double gate NMOS device. J. Theor. Appl. Inf. Technol. 90, 185–193 (2016)

    Google Scholar 

  18. Kaharudin, K.E., Hamidon, A.H., Salehuddin, F.: Design and optimization approaches in double gate device architecture. Int. J. Eng. Technol. 6, 6 (2014)

    Google Scholar 

  19. Kaharudin, K.E., Salehuddin, F., Zain, A.S.M., Aziz, M.N.I.A.: Impact of different dose, energy and tilt angle in source/drain implantation for vertical double gate PMOS device. J. Telecommun. Electron. Comput. Eng. 8, 23 (2016)

    Google Scholar 

  20. Montgomery, D.: Design and analysis of experiments. In: Blocking and Confounding in the 2k Factorial Design, 9th edn., pp. 306–344. Wiley, New York (2017)

    Google Scholar 

  21. Salehuddin, F., Kaharudin, K.E., Elgomati, H.A., Ahmad, I., Apte, P.R., Nopiah, Z.M., Zaharim, A.: Comparison of 2k-factorial and Taguchi method for optimization approach in 32 nm NMOS device. In: Mathematical Methods and Optimization Techniques in Engineering, pp. 125–134 (2013)

    Google Scholar 

Download references

Acknowledgements

The authors would like to thank the Ministry of Higher Education (MOHE) for sponsoring this work under project (FRGS/1/2017/TK04/FKEKK-CeTRI/F00335) and MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM) for the moral support throughout the project.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Ameer Farhan Roslan .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Roslan, A.F. et al. (2020). Comparisons in L32 2k-Factorial and L25 Taguchi for the 16 nm FinFET Statistical Optimization Applications. In: Jamaludin, Z., Ali Mokhtar, M.N. (eds) Intelligent Manufacturing and Mechatronics. SympoSIMM 2019. Lecture Notes in Mechanical Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-13-9539-0_41

Download citation

  • DOI: https://doi.org/10.1007/978-981-13-9539-0_41

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-9538-3

  • Online ISBN: 978-981-13-9539-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics