Abstract
The advancements in technology in this contemporary time require special computing devices to able to manage the increase of the computational power. However, the limitation of the sequential computing systems stands as an obstacle in fulfilling these requirements. Thus, the research community looking for a viable solution able to solve the grand computing problems. A parallel computing system is a collection of processing elements that cooperate and communicate to provide a fast solution for a problem. A new symmetric network named Shifted Peterson Network (SPN) has been proposed in this paper. The basic module (BM) of the suggested network is composed of ten nodes, and the BMs of SPN are connected through external nodes to construct an advanced level of this network. Furthermore, the connectivity of SPN is based on a shifting mechanism of the binary digits of each node. The architecture of SPN discussed in this paper, in addition, the static network performance parameters of this network has been evaluated and compared to popular conventional interconnection networks. The networks evaluated in terms of node degree, diameter, average distance, arc connectivity, bisection width, cost, wiring complexity, packing density, and message traffic density. SPN showed good results in almost all aspects compared to these networks. Therefore, SPN is a suitable choice for the massively parallel computer (MPC) systems.
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References
Rahman, M.M.H., Nor, R.M., Awal, M.R., Sembok, T.M.T., Miura, Y.: Long wire length of midimew-connected mesh network. In: Distributed Computing and Internet Technology, pp. 97–102 (2016)
Fu, H., Liao, J., Yang, J., Wang, L., Song, Z., Huang, X., Yang, C., Xue, W., Liu, F., Qiao, F., Zhao, W., Yin, X., Hou, C., Zhang, C., Ge, W., Zhang, J., Wang, Y., Zhou, C., Yang, G.: The sunway TaihuLight supercomputer: system and applications. Sci. China Inf. Sci. 59 (2016)
Rahman, M.M.H., Nor, R.M., Akhand, M.A.H., Sembok, T.M.T.: Cost effective factor of a midimew connected mesh network. Asian J. Sci. Res. 10(4) (2017)
Yunus, N.A.M., Othman, M., Mohd Hanapi, Z., Lun, K.Y.: Reliability review of interconnection networks. IETE Tech. Rev. 3(6), 596–606 (2016)
Ali, M.N.M., Rahman, M.M.H., Nor, R.M., Sembok, T.M.T.: A high radix hierarchical interconnection network for network-on-chip. In: 12th International Conference on Computing and Information Technology (IC2IT), Bangkok, Thailand (2016)
Mishra, B.S.P., Dehuri, S.: Parallel computing environments: a review. IETE Tech. Rev. 28(3), 240–247 (2011)
Sanchez, D., Michelogiannakis, G., Kozyrakis, C.: An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. (TACO) 7(1), 4 (2010)
Hag, A.A.Y., Rahman, M.M.H., Nor, R.M., Sembok, T.M.T.: Dynamic communication performance of a horizontal midimew connected mesh network. Int. J. Adv. Comput. Technol. 8(1), 31 (2016)
Khan, Z.A., Siddiqui, J., Samad, A.: Linear crossed cube (LCQ): a new interconnection network topology for massively parallel system. Int. J. Comput. Netw. Inf. Secur. (IJCNIS) 7(3), 18 (2015)
Rahman, M.M.H., Inoguchi, Y., Sato, Y., Miura, Y., Horiguchi, S.: Dynamic communication performance of a TESH network under the nonuniform traffic patterns Authors. In: 11th IEEE International Conference on Computer and Information Technology (ICCIT), pp. 365–370 (2008)
Rahman, M.M.H., Horiguchi, S.: Dynamic communication performance of a hierarchical torus network under non-uniform traffic patterns. IEICE Trans. Inf. Syst. 87(7), 1887–1896 (2004)
Faisal, F.A., Rahman, M.M.H., Inoguchi, Y.: A new power efficient high performance interconnection network for many-core processors. J. Parallel Distrib. Comput. 101, 92–102 (2017)
Ali, M.N.M., Rahman, M.M.H., Behera, D.K., Inoguchi, Y.: Static cost-effective analysis of a shifted completely connected network. In: Computational Intelligence in Data Mining, pp. 165–175. Springer, Singapore (2019)
Adhikari, N., Tripathy, C.R.: The folded crossed cube: a new interconnection network for parallel systems. Int. J. Comput. Appl. 4(3), 43–50 (2010)
Kim, J., Balfour, J., Dally, W.: Flattened butterfly topology for on-chip networks. In: 40th Annual IEEE/ACM International Symposium on Micro-architecture (Micro-40), pp. 172–182 (2007)
Valinataj, M., Mohammadi, S., Safari, S.: Fault-aware and reconfigurable routing algorithms for networks-on-chip. IETE J. Res. 57(3), 215–223 (2011)
Kim, J., Dally, W., Towles, B., Gupta, A.: Microarchitecture of a high-radix router. In: 32nd Annual International Symposium on Computer Architecture, vol. 33, pp. 420–431 (2005)
Amano, H.: Tutorial: introduction to interconnection networks from system area network to network on chips. In: 1st International Symposium on Computing and Networking, pp. 15–16 (2013)
Ahmed, A.B., Abdallah, A.B.: Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architectures. J. Parallel Distrib. Comput. 74(4), 2229–2240 (2014)
Rahman, M.M.H., Shah, A., Fukushi, M., Inoguchi, Y.: HTM: a new hierarchical interconnection network for future generation parallel computers. IETE Tech. Rev. 33(2), 93–104 (2016)
Kumar, J.M., Patnaik, L.M.: Extended hypercube: a hierarchical interconnection network of hypercubes. IEEE Trans. Parallel Distrib. Syst. 3(1), 45–57 (1992)
Moudi, M., Othman, M., Lun, K.Y., Rahiman, A.R.A.: x-folded TM: an efficient topology for interconnection networks. J. Netw. Comput. Appl. Elsevier 73, 27–34 (2016)
Prasad, N., Mukherjee, P., Chattopadhyay, S., Chakrabarti, I.: Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distrib. Comput. Elsevier 113, 17–36 (2018)
Candel, F., Petit, S., Sahuquillo, J., Duato, J.: Accurately modeling the on-chip and off-chip GPU memory subsystem. Future Gener. Comput. Syst. 82, 510–519 (2018)
Andujar, F.J., Villar, J.A., Sanchez, J.L., Alfaro, F.J., Duato, J.: N-dimensional twin torus topology. IEEE Trans. Comput. 64(10), 2847–2861 (2015)
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Hafizur Rahman, M.M., Ali, M.N.M., Olamide, O.A., Behera, D.K. (2020). Shifted Peterson Network: A New Network for Network-on-Chip. In: Das, A., Nayak, J., Naik, B., Pati, S., Pelusi, D. (eds) Computational Intelligence in Pattern Recognition. Advances in Intelligent Systems and Computing, vol 999. Springer, Singapore. https://doi.org/10.1007/978-981-13-9042-5_51
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