Abstract
Floating-point arithmetic units form the backbone of the state-of-the-art digital signal processing algorithms. Low power and area efficient design is always a key requirement for applications that use these algorithms. This requirement is more relevant for computationally intensive jobs that use higher-order multipliers. This paper attempts to study the possibility of addressing this issue using vedic arithmetic based floating-point unit. Vedic mathematics is an ancient Indian mathematics system that has come back to prominence in the last century. In this paper, we design a IEEE 754 single precision floating-point multiplier with the integer multiplication being carried out in a vedic mathematics style using different sutras. Nikhilam and Urdhva Tiryagbhyam sutras and their combination are used to design the same. This implementation is compared with conventional implementations using Booth and array multipliers. The designs are simulated using Verilog and synthesized using gpdk 90 nm technology. The results show that vedic multiplier based design gives competing results for multipliers of larger sizes. Low power and area efficient design is achieved for higher order multipliers when the design is based on the combination of Nikhilam and Urdhva Tiryagbhyam sutras. Thus for DSP applications using large multipliers, it is envisaged this approach of vedic multiplier design would lead to more efficient system implementations.
Keywords
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Andraka R (1998) A survey of CORDIC algorithms for FPGA based computers. In: Proceedings of the 1998 ACM/SIGDA sixth international symposium on field programmable gate arrays. ACM, pp 191–200
Hamid LSA, Shehata K, El-Ghitani H, El- Said M (2010) Design of generic floating point multiplier and adder/subtractor units. In: 2010 12th international conference on computer modelling and simulation (UKSim). IEEE, pp 615–618
Marcus G, Hinojosa P, Avila A, Nolazco-FIores J (2004) A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use. In: Proceedings of the fifth ieee international caracas conference on devices, circuits and systems, 2004, vol 1. IEEE, pp 319–323
Prabhu E, Mangalam H, Karthick S (2016) Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic. J Cent South Univ 23(7):1669–1681
M. M. Mano et al., “Computer system architecture,” 1982
Booth AD (1951) A signed binary multiplication technique. Q J Mech Appl Math 4(2):236–240
Al-Ashrafy M, Salem A, Anis W (2011) An efficient implementation of floating point multiplier. In: 2011 Saudi international electronics, communications and photonics conference (SIECPC). IEEE, pp 1–5
Ramteke P, Mhala N, Lakhe P (2014) An efficient implementation of double precision floating point multiplier using booth algorithm. Int J Adv Res Electr Electron Instrum Eng 3(7)
Tiwari HD, Gankhuyag G, Kim CM, Cho YB (2008) Multiplier design based on ancient indian vedic mathematics. In: ISOCC’08. international SoC design conference, 2008, vol 2. IEEE, pp II–65
Kanhe A, Das SK, Singh AK (2012) Design and implementation of floating point multiplier based on vedic multiplication technique. In: 2012 international conference on communication, information & computing technology (ICCICT), 2012, pp 19–20
Havaldar S, Gurumurthy K (2016) Design of vedic IEEE 754 floating point multiplier. In: IEEE international conference on recent trends in electronics, information & communication technology (RTEICT). IEEE, pp 1131–1135
Patel P, Shandilya A, Brahmbhatt N, Raval K, Deb D (2015) Vedic and conventional methods of n n binary multiplication with hardware implementation. In: International conference on smart sensors and systems (IC-SSS). IEEE, pp 1–6
Budhiraja H, Syed M, Ramya MA (2016) Verilog implementation of vedic multiplier. Int J Adv Eng Tech, Manag Appl Sci 3(5)
Jithin S, Prabhu E (2015) Parallel multiplier-accumulator unit based on vedic mathematics. ARPN J Eng Appl Sci 9(22):3608–3613
Zuras D, Cowlishaw M, Aiken A, Applegate M, Bailey D, Bass S, Bhandarkar D, Bhat M, Bindel D, Boldo S et al (2008) IEEE standard for floating-point arithmetic. IEEE Std 754-2008, pp 1–70
Rao YS, Kamaraju M, Ramanjaneyulu D (2015) An FPGA implementation of high speed and area efficient double-precision floating point multiplier using Urdhva Tiryagbhyam technique. In: 2015 conference on power, control, communication and computational technologies for sustainable growth (PCCCTSG). IEEE, pp 271–276
Bharath JSS, Tirathji K (1986) Vedic mathematics or sixteen simple sutras from the vedas. Motilal Banarsidas, Varanasi (India)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Loganathan, H., Rohit, P., Suneel, P.S., Balasubramanian, K. (2020). Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics. In: Hitendra Sarma, T., Sankar, V., Shaik, R. (eds) Emerging Trends in Electrical, Communications, and Information Technologies. Lecture Notes in Electrical Engineering, vol 569. Springer, Singapore. https://doi.org/10.1007/978-981-13-8942-9_39
Download citation
DOI: https://doi.org/10.1007/978-981-13-8942-9_39
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-8941-2
Online ISBN: 978-981-13-8942-9
eBook Packages: EngineeringEngineering (R0)