Abstract
Automatic correction of logical bugs in reversible circuits is discussed in this chapter. The general logic correction problem can be formulated as Quantified Boolean Formula (QBF) problem which can be solved by repeatedly applying SAT solvers. The automatic correction of reversible circuits can be similarly formulated as QBF. We show various experiments to demonstrate how the method can correct the circuits with an implementation on the logic synthesis and verification tool, ABC from University of California, Berkeley. The discussed methods can be extended to topologically constraints reversible circuit synthesis.
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Fujita, M. (2020). Automatic Error Correction of Reversible Circuits. In: Singh, A., Fujita, M., Mohan, A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore. https://doi.org/10.1007/978-981-13-8821-7_8
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DOI: https://doi.org/10.1007/978-981-13-8821-7_8
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