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Design and Testing of Reversible Logic pp 115–128Cite as

Reversible Circuit Synthesis Using Evolutionary Algorithms

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 577))

Abstract

With the unprecedented growth in VLSI technology in recent years, managing power dissipation has become a challenging task for many researchers. In this aspect, reversible logic emerges as one of the basis of future lossless computing system that promises zero energy dissipation, meanwhile classical physics cannot survive due to constant scaling of transistors and the exponential growth of transistor density in integrated circuits. It has applications in various domain such as low power VLSI, fault-tolerant designs, quantum computing, nanotechnology, DNA computing, optical computing, cryptography, and informatics. There are many existing works for the synthesis of reversible logic circuits; some are exact methods while others based on heuristic approaches. In this survey, we review a range of evolutionary computation approaches to the problem of optimal synthesis of reversible Logic—GA (Genetic Algorithm) based, PSO (Particle Swarm Optimization) based, ACO (Ant Colony Optimization)-based circuits where aim is to obtain a near-optimal solution by efficiently exploring the entire search space. This study provides an algorithmic review with comparative study on metaheuristic-based reversible logic synthesis methods proposed in existing literatures. Comparison of experimental results based on large number of benchmark circuits conform that evolutionary algorithms-based technique enables optimal or near-optimal solutions with lesser synthesis time.

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Authors and Affiliations

  1. Department of Electronics & Communication Engineering, NIT Kurukshetra, Kurukshetra, India

    T. N. Sasamal

  2. Department of Electronics & Communication Engineering, ABES Institute of Technology, Ghaziabad (Delhi NCR), India

    H. M. Gaur

  3. Department of Computer Applications, NIT Kurukshetra, Kurukshetra, India

    A. K. Singh

  4. Department of Electronics Engineering, IIT BHU, Varanasi, India

    A. Mohan

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  1. T. N. Sasamal
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  2. H. M. Gaur
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  3. A. K. Singh
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  4. A. Mohan
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Correspondence to T. N. Sasamal .

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Editors and Affiliations

  1. Department of Computer Applications, National Institute of Technology, Kurukshetra, India

    Ashutosh Kumar Singh

  2. VLSI Design and Education Center, University of Tokyo, Tokyo, Japan

    Masahiro Fujita

  3. Department of Electronics Engineering, Indian Institute of Technology, Varanasi, Uttar Pradesh, India

    Anand Mohan

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Sasamal, T.N., Gaur, H.M., Singh, A.K., Mohan, A. (2020). Reversible Circuit Synthesis Using Evolutionary Algorithms. In: Singh, A., Fujita, M., Mohan, A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore. https://doi.org/10.1007/978-981-13-8821-7_7

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  • DOI: https://doi.org/10.1007/978-981-13-8821-7_7

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