Abstract
Recently, reversible logic computation has attracted researchers’ attention for implementing low-power digital logic designs. In fact, no information is wasted in this approach, i.e., it performs a bijective function. This chapter introduces a hardware design of reversible BinDCT. It is a new proposal in reversible approach. In this study, we dealt with a variety of sub-modules, which have a better performance in terms of constant inputs (CIs), garbage output (GO), power and quantum cost (QC) as well as the delay than that of existing designs. This work can offer a vital step in the design of reversible designs for in the field of image processing. It could also be present as an essential step in this area since the image processing systems are known to be the biggest energy consumers.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Landauer R (1961) Irreversibility and heat generation in computing process. IBM J Res Dev 183–191
Bennett CH (1973) Logical reversibility of computation IBM J Res Dev 525–532
Shende VV, Prasad AK, Markov IL (2003) Synthesis of reversible logic circuits. IEEE Trans CAD 710–722
Knill E, Laflamme R, Milburn GJ (2001) A scheme for efficient quantum computation with linear optics. Nature 46–52
Chandana S, Navya C, Nagamani AN (2016) Design of register file using re versible logic. IEEE Int Conf Circuit Power Comput Technol (ICCPCT)
Chenga CS, Singh AK, Gopala L (2015) Efficient three variables reversible logic synthesis using mixed polarity Toffoli gate. Procedia Comput Sci 362–368
Maslov D, Dueck GW, Miller M (2008) Quantum circuit simplification and level compaction. IEEE Trans Comput-Aided Des. Integr. Circuits Syst 436–444
Saeedi M, Markov IL (2014) Synthesis and optimization of reversible circuits a survey. ACM Comput Surv (CSUR) 1–34
Cheng CS, Singh AK (2015) Heuristic synthesis of reversible logic–a comparative study. Adv Electr Electron Eng 210–225
Babu HM, Islam MR, Chowdhury AR, Chowdhury SMA (2004) Synthesis of full-adder circuit using reversible logic. In: 17th International conference on VLSI design, pp 757–760
Thapliyal H, Ranganathan N (2013) Design of efficient reversible logic-based binary and BCD adder circuits. ACM J Emerg Technol Comput Syst 1–31
Biswas AK, Hasan MM, Chowdhury AR, Babu HMH. (2008) Efficient approaches for designing reversible binary coded decimal adders. Microelectron J 1693–1703
Nagamani A, Ashwin S, Vinod KA (2014) Design of optimized reversible binary adder/subtractor and BCD adder. In: International conference on contemporary computing and informatics (IC3I)
Moghadam MZ, Navi K (2012) Ultra-area-efficient reversible multiplier. Microelectron. J 377–385
Morrison M, Ranganathan N (2011) Design of a reversible ALU based on novel programmable reversible logic gate structures. In: IEEE computer society annual symposium on VLSI
Rangaraju HG, Hegde V, Raja KB, Muralidhara KN (2012) Design of efficient reversible binary comparator. In: International conference on communication technology and system design, pp 897–904
Morrison M, Lewandowski M, Ranganathan N (2012) Design of a tree-based comparator and memory unit based on a novel reversible logic structure. In: IEEE Computer Society Annual Symposium on VLSI, pp 331–336
Antonino T, Matteo M, Gianluca P, Fabrizio F, Donatella S (2007) Pipelined fast 2D-DCT accelerator for FPGA-based SoCs. In: IEEE Computer Society Annual Symposium on VLSI, pp 9–11
Primechaev S, Frolov A, Simak B (2007) Scene changedetection using DCT features in transform domain videoindexing. In: 14th International workshop systems, signals and image processing and 6th EURASIP conference focused on speech and image processing, multi media communications and services, pp 369–372
Murphy C, Harvey M (2002) Reconfigurable hardware implementation of BinDCT. Electron Lett 1012–1013
Liang J, Tran T (2001) Fast multiplierless approximations of the DCT with the lifting scheme. IEEE Trans Signal Process 3032–3044
Philip PD, Paul MC, Truong QN (2005) BinDCT and its efficient VLSI Architectures for real-time embedded applications. J Imaging Sci Technol 124–137
Mahmoud FK (2007) Image compression using BinDCT for dynamic hardware FPGA’s, thesis. Liverpool John Moores University
Abdessalem BA, Ichraf C, Abdellatif M (2016) Efficient BinDCT hardware architecture exploration and implementation on FPGA. J Adv Res 909–922
Lamjed T, Bouraoui O (2017) Design of hardware RGB to HMMD converter based on reversible logic. IET Image Process 646–655
Bikash D, Jadav CD, Debashis D (2017) Reversible logic-based image ste ganography using quantum dot cellular automata for secure nanocommunication. IET Circuits Devices Syst 1–10
Toffoli T (1980) Reversible computing. Technical memo MIT/LCS/TM-151, MIT lab for computer science
Feynman RP (1985) Quantum mechanical computers. Opt News 11–20
Chanderkanta AB, Santosh K (2017) Ultrafast optical reversible double Feynman logic gate using electro-optic effect in lithium-niobate based Mach Zehnder interferometers. In: Proceeding of SPIE, oxide-based materials and devices VIII, vol 10105, pp 1010520
Moraga C (2014) Mixed polarity reversible peresgates. IET Electron. Lett 987–989
Kaye P, Laflamme R, Mosca M (2007) An introduction to quantum computing Oxford University Press, Oxford, eBook-LinG, ISBN 0-19-857000-7
Fredkin E, Toffoli T (1982) Conservative logic. Int J Theoreical Phys 219–253
Mohammadi M, Eshghi M, Haghparast M, Bahrololoom A (2008) Design and optimization of reversible BCD adder/subtractor circuit for quantum and nanotechnology based systems. World Appl Sci J 787–792
Haghparast M, Navi K (2008) A novel reversible BCD adder for nanotechnology based systems. Am J Appl Sci 282–288; Peres A (1985) Reversible logic and quantum computers. Phys Rev A 3266–3276
Ali NB, Sajjad W, Nazir H (2015) A new approach of presenting reversible logic gate in nanoscale. SpringerPlus 153
Guowu Y, Hung WNN, Xiaoyu S (2005) Majority-based reversible logic gates. Theor. Comput. Sci, 259–274
Lenin G, Nor S, Mohd M (2014) Design and synthesis of reversible arithmetic and logic unit (ALU). In: IEEE conference computer, communications, and control technology (I4CT)
Stolze J, Suter D (2004) Quantum computing: a short course from theory to experiment. Wiley, Weinheim
Bruce J, Thornton M, Shivakumaraiah L, Kokate P, Li X (2002) Efficient adder circuits based on a conservative reversible logic gate. In: Proceedings IEEE computer society annual symposium on VLSI, pp 74–79
Murphy C, Harvey M (2002) Reconfigurable hardware implementation BinDCT. Electron Lett 1012–1013
Rangaraju HG, Venugopal U, Muralidhara KN, Raja KB (2010) Low power reversible parallel binary adder/subtractor. Int J VLSI Des Commun Syst 23–34
Shekoofeh M, Mohammad R, Reshadinezhad (2015) A Novel 4x4 Universal reversible gate as a cost efficient full adder/subtractor in terms of re versible and quantum metrics. Int J Mod Educ Comput Sci 28–34
Microwind DSCH—schematic editor and digital simulator. http://www.microwind.net/dsch.ph
Thersesal T, Sathish K, Aswinkumor R (2015) A new design of optical reversible adder and subtractor using MZI. Int J Sci Res Publ 1–6
Gupta A, Singla P, Gupta J, Maheshwari N (2013) An improved structure of reversible adder and subtractor. Int J Electron Comput Sci Eng 712–718
Shamsujjoha MH, Hasan M, Lafifa J (2013) Design of a compact reversible fault tolerant field programmable gate array: a novel approach in reversible logic synthesis. Microelectron J 519–537
Nazma TH, Hasan, BM, Lafifa J (2017) Power efficient optimum design of the reversible plessey logic block of a field-programmable gate array. J Sustain Comput 1–35
Dastan F, Haghparas M (2012) A novel nanometric reversible signed divider with overflow checking capability. Res J Appl Sci Eng Technol 535–543
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this chapter
Cite this chapter
Gassoumi, I., Touil, L., Ouni, B. (2020). Design of Reversible Hardware BinDCT. In: Singh, A., Fujita, M., Mohan, A. (eds) Design and Testing of Reversible Logic. Lecture Notes in Electrical Engineering, vol 577. Springer, Singapore. https://doi.org/10.1007/978-981-13-8821-7_2
Download citation
DOI: https://doi.org/10.1007/978-981-13-8821-7_2
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-8820-0
Online ISBN: 978-981-13-8821-7
eBook Packages: EngineeringEngineering (R0)