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Towards Spintronics Nonvolatile Caches

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Applications of Emerging Memory Technology

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 63))

Abstract

Non-volatile (NV) cache is desired for overcoming the power and speed bottlenecks of the modern static random access memory (SRAM). A promising candidate for constructing the NV cache is the spin transfer torque magnetic RAM (STT-MRAM), which is featured with low power, fast speed, high density and nearly unlimited endurance. In this chapter, we will review the efforts made to realize the STT-MRAM based NV cache, ranging from architecture to device levels. In addition, the application potential of emerging spintronics technologies, such as spin orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA), will be discussed in terms of their benefits and challenges.

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References

  1. G. Prenat, K. Jabeur, P. Vanhauwaert, G. Pendina, F. Oboril, R. Bishnoi, M. Ebrahimi, N. Lamard, O. Boulle, K. Garello, J. Langer, B. Ocker, M. Cyrille, P. Gambardella, M. Tahoori, G. Gaudin, Ultra-fast and high-reliability SOT-MRAM: from cache replacement to normally-off computing. IEEE Trans. Multi-Scale Comput. Syst. 2(1), 49–60 (2016)

    Article  Google Scholar 

  2. Inside NAND Flash Memories (Springer, Dordrecht, The Netherlands, 2010)

    Google Scholar 

  3. H. Wong, S. Raoux, S. Kim, J. Liang, J. Reifenberg, B. Rajendran, M. Asheghi, K. Goodson, Phase change memory. Proc. IEEE 98(12), 2201–2227 (2010)

    Article  Google Scholar 

  4. M. Qazi, M. Clinton, S. Bartling, A. Chandrakasan, A low-voltage 1 Mb FRAM in 0.13 μm CMOS featuring time-to-digital sensing for expanded operating margin. IEEE J. Solid-State Circuits 47(1), 141–150 (2012)

    Article  Google Scholar 

  5. D. Apalkov, B. Dieny, J. Slaughter, Magnetoresistive random access memory. Proc. IEEE 104(10), 1796–1830 (2016)

    Article  Google Scholar 

  6. S. Bhatti, R. Sbiaa, A. Hirohata, H. Ohno, S. Fukami, S. Piramanayagam, Spintronics based random access memory: a review. Mater. Today 20(9), 530–548 (2017)

    Article  Google Scholar 

  7. H. Akinaga, H. Shima, Resistive random access memory (ReRAM) based on metal oxides. Proc. IEEE 98(12), 2237–2251 (2010)

    Article  Google Scholar 

  8. H. Noguchi, et al., 4 MB STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write/read-modify-write scheme, in IEEE-ISSCC (2016), pp. 132–133

    Google Scholar 

  9. H. Noguchi, et al., 7.5 A 3.3 ns-access-time 71.2 μW/MHz 1 Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture, in IEEE-ISSCC (2015), pp. 1–3

    Google Scholar 

  10. A.D. Kent, D. Worledge, A new spin on magnetic memories. Nat. Nanotechnol. 10(3), 187–191 (2015)

    Article  Google Scholar 

  11. B. Engel, J. Akerman, B. Butcher, R. Dave, M. DeHerrera, M. Durlam, G. Grynkewich, J. Janesky, S. Pietambaram, N. Rizzo, J. Slaughter, K. Smith, J. Sun, S. Tehrani, A 4-Mb toggle MRAM based on a novel bit and switching method. IEEE Trans. Magn. 41(1), 132–136 (2005)

    Article  Google Scholar 

  12. L. Berger, Emission of spin waves by a magnetic multilayer traversed by a current. Phys. Rev. B 54(13), 9353–9358 (1996)

    Article  Google Scholar 

  13. J. Slonczewski, Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159(1–2), L1–L7 (1996)

    Article  Google Scholar 

  14. Y. Huai, F. Albert, P. Nguyen, M. Pakala, T. Valet, Observation of spin-transfer switching in deep submicron-sized and low-resistance magnetic tunnel junctions. Appl. Phys. Lett. 84(16), 3118–3120 (2004)

    Article  Google Scholar 

  15. Everspin Technologies

    Google Scholar 

  16. W. Zhao, C. Chappert, V. Javerliac, J. Noziere, High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits. IEEE Trans. Magn. 45(10), 3784–3787 (2009)

    Article  Google Scholar 

  17. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, T. Zhang, A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme. IEEE J. Solid-State Circuits 47(2), 560–573 (2012)

    Article  Google Scholar 

  18. W. Kang, L. Zhang, J.O. Klein, Y. Zhang, D.R. Ravolosona, W. Zhao, Reconfigurable codesign of STT-MRAM under process variations in deeply scaled technology. IEEE Trans. Electron Devices 62(6), 1769–1777 (2015)

    Article  Google Scholar 

  19. S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H.D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, H. Ohno, A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction. Nat. Mater. 9(9), 721–724 (2010)

    Article  Google Scholar 

  20. M. Hosomi, et al., A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM, in IEEE-IEDM (2005), pp. 459–462

    Google Scholar 

  21. A. Maashri, G. Sun, X. Dong, V. Narayanan, Y. Xie, 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis, in IEEE-ICCD (2009), pp. 254–259

    Google Scholar 

  22. G. Sun, X. Dong, Y. Xie, J. Li, Y. Chen, A novel architecture of the 3D stacked MRAM L2 cache for CMPs, in IEEE-HPCA (2009), pp. 239–249

    Google Scholar 

  23. X. Dong, et al., Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, in ACM/IEEE DAC (2008), pp. 554–559

    Google Scholar 

  24. G. Jan, et al., Demonstration of fully functional 8 Mb perpendicular STT-MRAM chips with sub-5 ns writing for non-volatile embedded memories, in IEEE Symposium on VLSI Technology (2014), pp. 42–43

    Google Scholar 

  25. D. Saida, et al., Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS, in IEEE Symposium on VLSI Technology (2016), pp. 1–2

    Google Scholar 

  26. G. Jan, et al., Achieving sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms, in IEEE Symposium on VLSI Technology (2016), pp. 1–2

    Google Scholar 

  27. D. Saida, S. Kashiwada, M. Yakabe, T. Daibou, M. Fukumoto, S. Miwa, Y. Suzuki, K. Abe, H. Noguchi, J. Ito, S. Fujita, 1x–2x nm perpendicular MTJ switching at sub-3-ns pulses below 100 µA for high-performance embedded STT-MRAM for sub-20-nm CMOS. IEEE Trans. Electron Devices 64(2), 427–431 (2017)

    Article  Google Scholar 

  28. P. Zhou, B. Zhao, J. Yang, Y. Zhang, Energy reduction for STT-RAM using early write termination, in IEEE/ACM ICCAD (2009), pp. 264–268

    Google Scholar 

  29. J. Wang, X. Dong, Y. Xie, OAP: an obstruction-aware cache management policy for STT-RAM last-level caches, in DATE (2013), pp. 847–852

    Google Scholar 

  30. C.J. Lin, et al., 45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell, in IEEE-IEDM (2009), pp. 1–4

    Google Scholar 

  31. K. Ikegami, et al., Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques, in IEEE-IEDM (2014), pp. 28.1.1–28.1.4

    Google Scholar 

  32. G. Sun, Y. Zhang, Y. Wang, Y. Chen, Improving energy efficiency of write-asymmetric memories by log style write, in ISLPED (2012), pp. 173–178

    Google Scholar 

  33. X. Wu, J. Li, L. Zhang, E. Speight, Y. Xie, Power and performance of read-write aware hybrid caches with non-volatile memories, in DATE (2009), pp. 737–742

    Google Scholar 

  34. J. Li, C. Xue, Y. Xu, STT-RAM based energy-efficiency hybrid cache for CMPs, in IEEE/IFIP VLSI-SoC (2011), pp. 31–36

    Google Scholar 

  35. K. Qiu, M. Zhao, Q. Li, C. Fu, C. Xue, Migration-aware loop retiming for STT-RAM-based hybrid cache in embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3), 329–342 (2014)

    Article  Google Scholar 

  36. A. Sharifi, M. Kandemir, Automatic feedback control of shared hybrid caches in 3D chip multiprocessors, in International Euromicro Conference on PDP (2011), pp. 393–400

    Google Scholar 

  37. B. Wu, Y. Cheng, J. Yang, A. Todri-Sanial, W. Zhao, Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65(4), 1755–1768 (2016)

    Article  Google Scholar 

  38. B. Wu, et al., Thermosiphon: a thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs, in IEEE/ACM ICCAD (2017), pp. 474–481

    Google Scholar 

  39. C. Kim, D. Burger, S.W. Keckler, An Adaptive, non-uniform cache structure for wire-delay dominated on-chip caches, in ACM-ASPLOS (2002), pp. 211–222

    Article  Google Scholar 

  40. W. Zhao et al., Failure and reliability analysis of STT-MRAM. Microelectron. Reliab. 52(9–10), 1848–1852 (2011)

    Google Scholar 

  41. D. Zhang, L. Zeng, T. Gao, F. Gong, X. Qin, W. Kang, Y. Zhang, Y. Zhang, J. Klein, W. Zhao, Reliability-enhanced separated pre-charge sensing amplifier for hybrid CMOS/MTJ logic circuits. IEEE Trans. Magn. 53(9), 1–5 (2017)

    Article  Google Scholar 

  42. H. Zhang, W. Kang, T. Pang, W. Lv, Y. Zhang, W. Zhao, Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM, in IEEE/ACM NANOARCH (2016), pp. 1–6

    Google Scholar 

  43. L. Zhang, et al., Channel modeling and reliability enhancement design techniques for STT-MRAM, in ISVLSI (2015), pp. 461–466

    Google Scholar 

  44. M. McCartney, SRAM reliability improvement using ECC and circuit techniques, Ph.D. thesis (2014)

    Google Scholar 

  45. X. Wang, M. Mao, E. Eken, W. Wen, H. Li, Y. Chen, Sliding basket: an adaptive ECC scheme for runtime write failure suppression of STT-RAM cache, in DATE (2016), pp. 762–767

    Google Scholar 

  46. X. Dong, C. Xu, Y. Xie, N. Jouppi, NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7), 994–1007 (2012)

    Article  Google Scholar 

  47. S. Wilton, N. Jouppi, CACTI: an enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31(5), 677–688 (1996)

    Article  Google Scholar 

  48. B. Wu, et al., An architecture-level cache simulation framework supporting advanced PMA STT-MRAM, in IEEE/ACM NANOARCH (2015), pp. 7–12

    Google Scholar 

  49. E. Eken, et al., NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation, in ACM/EDAC/IEEE-DAC (2016), pp. 1–6

    Google Scholar 

  50. K. Abe, et al., Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU, in IEEE-IEDM (2012), pp. 10.5.1–10.5.4

    Google Scholar 

  51. S. Yamamoto, S. Sugahara, Nonvolatile static random access memory using magnetic tunnel junctions with current-induced magnetization switching architecture. Jpn. J. Appl. Phys. 48(4), 043001 (2009)

    Article  Google Scholar 

  52. T. Ohsawa, et al., 1 Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0 ns/200 ps wake-up/power-off times, in Symposium on VLSIC (2012), pp. 46–47

    Google Scholar 

  53. H. Noguchi, et al., A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors, in Symposium on VLSI Technology (2013), pp. 108–109

    Google Scholar 

  54. H. Noguchi, et al., Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU, in Symposium on VLSIC (2014), pp. 1–2

    Google Scholar 

  55. A. Kawasumi, et al., Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory, in IEEE-IMW (2013), pp. 76–79

    Google Scholar 

  56. L. Xue, B. Wu, B. Zhang, Y. Cheng, P. Wang, C. Park, J. Kan, S. Kang, Y. Xie, An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(3), 484–495 (2018)

    Article  Google Scholar 

  57. M. Wang, W. Cai, K. Cao, J. Zhou, J. Wrona, S. Peng, H. Yang, J. Wei, W. Kang, Y. Zhang, J. Langer, B. Ocker, A. Fert, W. Zhao, Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance. Nat. Commun. 9(1) (2018)

    Google Scholar 

  58. K. Ikegami, et al., MTJ-based ‘normally-off processors’ with thermal stability factor engineered perpendicular MTJ L2 cache based on 2T-2MTJ cell L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme, in IEEE-IEDM (2015), pp. 25.1.1–25.1.4

    Google Scholar 

  59. C.W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, M.R. Stan, Relaxing non-volatility for fast and energy-efficient STT-RAM caches, in IEEE-HPCA (2011), pp. 50–61

    Google Scholar 

  60. H. Li, X. Wang, Z. Ong, W. Wong, Y. Zhang, P. Wang, Y. Chen, Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement. IEEE Trans. Magn. 47(10), 2356–2359 (2011)

    Article  Google Scholar 

  61. A. Jog, et al., Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs, in DAC (2012), pp. 243–252

    Google Scholar 

  62. Z. Sun, et al., Multi retention level STT-RAM cache designs with a dynamic refresh scheme, in IEEE/ACM MICRO (2011), pp. 329–338

    Google Scholar 

  63. I. Miron, K. Garello, G. Gaudin, P. Zermatten, M. Costache, S. Auffret, S. Bandiera, B. Rodmacq, A. Schuhl, P. Gambardella, Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection. Nature 476(7359), 189–193 (2011)

    Article  Google Scholar 

  64. L. Liu, C. Pai, Y. Li, H. Tseng, D. Ralph, R. Buhrman, Spin-torque switching with the giant spin Hall effect of tantalum. Science 336(6081), 555–558 (2012)

    Article  Google Scholar 

  65. M. Cubukcu, O. Boulle, M. Drouard, K. Garello, C. Onur Avci, I. Mihai Miron, J. Langer, B. Ocker, P. Gambardella, G. Gaudin, Spin-orbit torque magnetization switching of a three-terminal perpendicular magnetic tunnel junction. Appl. Phys. Lett. 104(4), 042406 (2014)

    Article  Google Scholar 

  66. Z. Wang, Z. Li, Y. Liu, S. Li, L. Chang, W. Kang, Y. Zhang, W. Zhao, Progresses and challenges of spin orbit torque driven magnetization switching and application, in IEEE-ISCAS (2018)

    Google Scholar 

  67. M. Cubukcu, O. Boulle, N. Mikuszeit, C. Hamelin, T. Bracher, N. Lamard, M. Cyrille, L. Buda-Prejbeanu, K. Garello, I. Miron, O. Klein, G. de Loubens, V. Naletov, J. Langer, B. Ocker, P. Gambardella, G. Gaudin, Ultra-fast perpendicular spin-orbit torque MRAM. IEEE Trans. Magn. 54(4), 1–4 (2018)

    Article  Google Scholar 

  68. J. Kim, et al., Spin-Hall effect MRAM based cache memory: a feasibility study, in DRC (2015), pp. 117–118

    Google Scholar 

  69. R. Bishnoi, M. Ebrahimi, F. Oboril, M.B. Tahoori, Architectural aspects in design and analysis of SOT-based memories, in ASP-DAC (2014), pp. 700–707

    Google Scholar 

  70. Z. Wang, L. Zhang, M. Wang, Z. Wang, D. Zhu, Y. Zhang, W. Zhao, High-density NAND-like spin transfer torque memory with spin orbit torque erase operation. IEEE Electron Device Lett. 39(3), 343–346 (2018)

    Article  Google Scholar 

  71. H. Yoda, et al., Voltage-control spintronics memory (VoCSM) having potentials of ultra-low energy-consumption and high-density, in IEEE-IEDM (2016), pp. 27.6.1–27.6.4

    Google Scholar 

  72. Z. Wang, W. Zhao, E. Deng, J. Klein, C. Chappert, Perpendicular-anisotropy magnetic tunnel junction switched by spin-Hall-assisted spin-transfer torque. J. Phys. D Appl. Phys. 48(6), 045001 (2015)

    Article  Google Scholar 

  73. A. van den Brink, S. Cosemans, S. Cornelissen, M. Manfrini, A. Vaysset, W. Van Roy, T. Min, H. Swagten, B. Koopmans, Spin-Hall-assisted magnetic random access memory. Appl. Phys. Lett. 104(1), 012403 (2014)

    Article  Google Scholar 

  74. L. Chang, et al., Evaluation of spin-Hall-assisted STT-MRAM for cache replacement, in IEEE/ACM NANOARCH (2016), pp. 73–78

    Google Scholar 

  75. M. Wang et al., Field-free switching of a perpendicular magnetic tunnel junction through the interplay of spin–orbit and spin-transfer torques. Nat. Electron. 1, 582–588 (2018)

    Article  Google Scholar 

  76. Z. Wang et al., Proposal of Toggle Spin Torques Magnetic RAM for Ultrafast Computing. IEEE Electron Device Lett 40(5), 726–729 (2019)

    Article  Google Scholar 

  77. S. Fukami, C. Zhang, S. DuttaGupta, A. Kurenkov, H. Ohno, Magnetization switching by spin–orbit torque in an antiferromagnet–ferromagnet bilayer system. Nat. Mater. 15(5), 535–541 (2016)

    Article  Google Scholar 

  78. Y. Oh, S. Chris Baek, Y. Kim, H. Lee, K. Lee, C. Yang, E. Park, K. Lee, K. Kim, G. Go, J. Jeong, B. Min, H. Lee, K. Lee, B. Park, Field-free switching of perpendicular magnetization through spin–orbit torque in antiferromagnet/ferromagnet/oxide structures. Nat. Nanotechnol. 11(10), 878–884 (2016)

    Article  Google Scholar 

  79. W. Wang, M. Li, S. Hageman, C. Chien, Electric-field-assisted switching in magnetic tunnel junctions. Nat. Mater. 11(1), 64–68 (2011)

    Article  Google Scholar 

  80. J.G. Alzate, et al., Voltage-induced switching of nanoscale magnetic tunnel junctions, in IEEE-IEDM (2012), pp. 29.5.1–29.5.4

    Google Scholar 

  81. K. Wang, H. Lee, P.Khalili Amiri, Magnetoelectric random access memory-based circuit design by using voltage-controlled magnetic anisotropy in magnetic tunnel junctions. IEEE Trans. Nanotechnol. 14(6), 992–997 (2015)

    Article  Google Scholar 

  82. W. Kang, Y. Ran, Y. Zhang, W. Lv, W. Zhao, Modeling and exploration of the voltage-controlled magnetic anisotropy effect for the next-generation low-power and high-speed MRAM applications. IEEE Trans. Nanotechnol. 16(3), 387–395 (2017)

    Article  Google Scholar 

  83. W. Kang, L. Chang, Y. Zhang, W. Zhao, Voltage-controlled MRAM for working memory: perspectives and challenges, in DATE (2017), pp. 542–547

    Google Scholar 

  84. S. Kanai, Y. Nakatani, M. Yamanouchi, S. Ikeda, H. Sato, F. Matsukura, H. Ohno, Magnetization switching in a CoFeB/MgO magnetic tunnel junction by combining spin-transfer torque and electric field-effect. Appl. Phys. Lett. 104(21), 212406 (2014)

    Article  Google Scholar 

  85. H. Xu, Y. Li, R. Melhem, A.K. Jones, Multilane racetrack caches: improving efficiency through compression and independent shifting, in ASP-DAC (2015), pp. 417–422

    Google Scholar 

  86. X. Zhang, L. Zhao, Y. Zhang, J. Yang, Exploit common source-line to construct energy efficient domain wall memory based caches, in IEEE-ICCD (2015), pp. 157–163

    Google Scholar 

  87. R. Venkatesan et al., Cache design with domain wall memory. IEEE Trans. Comput. 65(4), 1010–1024 (2016)

    Article  MathSciNet  Google Scholar 

  88. W. Kang, C. Zheng, Y. Huang, X. Zhang, W. Lv, Y. Zhou, W. Zhao, Compact modeling and evaluation of magnetic skyrmion-based racetrack memory. IEEE Trans. Electron Devices 64(3), 1060–1068 (2017)

    Article  Google Scholar 

  89. W. Kang, Y. Huang, X. Zhang, Y. Zhou, W. Zhao, Skyrmion-electronics: an overview and outlook. Proc. IEEE 104(10), 2040–2061 (2016)

    Article  Google Scholar 

  90. F. Chen et al. Process variation aware data management for magnetic skyrmions racetrack memory, in ASP-DAC (2018), pp. 221–226

    Google Scholar 

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (61704005, 61501013 and 61571023), the National Key Technology Program of China (2017ZX01032101), and the International Mobility Project (B16001 and 2015DFE12880).

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Authors and Affiliations

  1. School of Microelectronics, Beijing Advanced Innovation Center for Big Data and Brain Computing (BDBC), Fert Beijing Research Institute, Beihang University, Beijing, 100191, China

    Zhaohao Wang, Chao Wang, Wang Kang & Weisheng Zhao

  2. School of Electronics and Information Engineering, Fert Beijing Research Institute, Beihang University, Beijing, 100191, China

    Bi Wu

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  1. Zhaohao Wang
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Correspondence to Zhaohao Wang .

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  1. Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India

    Manan Suri

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Wang, Z., Wu, B., Wang, C., Kang, W., Zhao, W. (2020). Towards Spintronics Nonvolatile Caches. In: Suri, M. (eds) Applications of Emerging Memory Technology. Springer Series in Advanced Microelectronics, vol 63. Springer, Singapore. https://doi.org/10.1007/978-981-13-8379-3_1

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