PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution

  • Sukanta DeyEmail author
  • Sukumar Nandi
  • Gaurav Trivedi
Part of the Studies in Computational Intelligence book series (SCI, volume 784)


Power grid network (PGN) of a VLSI system-on-chip (SoC) occupies a significant amount of routing area in a chip. As the number of functional blocks is increasing in an SoC chronologically, the need of the hour is to have more power lines in order to provide adequate power connections to the extra-added functional blocks. Therefore, to accommodate more functional blocks in the minimum area possible, the PGN should also have minimum area. Minimization of the area can be achieved by relaxing few power grid constraints. In view of this, due to the resistance of the PGN, it suffers from considerable reliability issues such as voltage drop noise and electromigration. Further, it also suffers from the interconnect delay and power dissipation due to its parasitic resistances and capacitances. These PGN constraints should be relaxed up to a certain limit, and the area minimization should be done accordingly. Therefore, in this paper, we have considered an RC model of the PGN and formulated the area minimization for PGN as a large-scale minimization problem considering different reliability, delay, and power-aware constraints. Evolutionary computation-based cooperative coevolution technique has been used to solve this large-scale minimization problem. The proposed method is tested on industry-based power grid benchmarks. It is observed that significant metal routing area of the PGN has been reduced using the proposed method.


Area minimization Cooperative coevolution Delay Evolutionary computation Large-scale optimization Power grid networks Reliability VLSI 


  1. 1.
    Dey, S., Nandi, S., Trivedi, G.: Markov chain model using Lévy flight for VLSI power grid analysis. In: Proceedings of VLSID, pp. 107–112 (2017)Google Scholar
  2. 2.
    Tan, S.X.D., Shi, C.J.R., Lee, J.C.: Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE TCAD 22(12), 1678–1684 (2003)Google Scholar
  3. 3.
    Wang, T.Y., Chen, C.P.: Optimization of the power/ground network wire-sizing and spacing based on sequential network simplex algorithm. In: Proceedings of ISQED, pp. 157–162 (2002)Google Scholar
  4. 4.
    Zeng, Z., Li, P.: Locality-driven parallel power grid optimization. IEEE TCAD 28(8), 1190–1200 (2009)Google Scholar
  5. 5.
    Zhou, H., Sun, Y., Tan, S.X.D.: Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires. In: Proceedings of ASP-DAC, pp. 399–404 (2018)Google Scholar
  6. 6.
    Dey, S., Nandi, S., Trivedi, G.: PGIREM: reliability-constrained IR drop minimization and electromigration assessment of VLSI power grid networks using cooperative coevolution. In: Proceedings of ISVLSI (2018)Google Scholar
  7. 7.
    Butcher, J.C.: Numerical Methods for Ordinary Differential Equations. Wiley (2016)Google Scholar
  8. 8.
    Potter, M.A., Jong, K.A.D.: Cooperative coevolution: an architecture for evolving coadapted subcomponents. Evol. Comput. 8(1), 1–29 (2000)CrossRefGoogle Scholar
  9. 9.
    Potter, M.A., De Jong, K.A.: A CC approach to function optimization. In: Proceedings of PPSN, pp. 249–257 (1994)Google Scholar
  10. 10.
    Liu, Y., Higuchi, T.: Scaling up fast evolutionary programming with CC. Proceedings of CEC, vol. 2, pp. 1101–1108 (2001)Google Scholar
  11. 11.
    Van den Bergh, F.: A cooperative approach to PSO. IEEE TEC 8(3), 225–239 (2004)Google Scholar
  12. 12.
    Shi, Y.J., Li, Z.Q.: Cooperative co-evolutionary DE for function optimization. In: Advances in Natural Computation, p. 428. Springer (2005)Google Scholar
  13. 13.
    Yang, Z., Yao, X.: Large scale evolutionary optimization using CC. Elsevier Inf. Sci. 178(15), 2985–2999 (2008a)Google Scholar
  14. 14.
    Yang, Z., Yao, X.: Self-adaptive DE with neighborhood search. In: Proceedings of CEC, pp. 1110–1116 (2008b)Google Scholar
  15. 15.
    Omidvar, M.N., Yao, X.: Cooperative co-evolution for large scale optimization through more frequent random grouping. In: IEEE CEC, pp. 1–8 (2010)Google Scholar
  16. 16.
    Davis, T.A.: KLU, a direct sparse solver for circuit simulation problems. ACM TOMS 37(3), 36 (2010)CrossRefGoogle Scholar
  17. 17.
    Nassif, S.R.: Power grid analysis benchmarks. In: Proceedings of ASP-DAC, pp. 376–381 (2008)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of CSEIIT GuwahatiAmingaon, North GuwahatiIndia
  2. 2.Department of EEEIIT GuwahatiAmingaon, North GuwahatiIndia

Personalised recommendations