Abstract
Arithmetic logic unit (ALU) is a building block of many digital calculating systems like calculator, cell phone, computer, processors, etc. In present electronic market as technology is upgrading day by day, fast-growing technologies with portable devices demand for low-power VLSI design. Demand for less delay and low area is increasing. Reversible logic circuit helps in reduction of power dissipation. ALU is designed with both reversible and irreversible logic gates to reduce power and delay. This type of design can be named as hybrid ALU. In digital adder, time taken to propagate carry is decreased by using carry select adder (CSA) and Kogge–Stone adder (KSA), and area is reduced by using binary-to-excess-one converter (BEC) instead of ripple carry adder (RCA). This adder design is used in Vedic multiplier to add partial products, which also reduce delay in digital multiplier.
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Shirol, S.B., Ramakrishna, S., Shettar, R.B. (2019). A Novel Design and Implementation of 32-Bit Hybrid ALU. In: Peng, SL., Dey, N., Bundele, M. (eds) Computing and Network Sustainability. Lecture Notes in Networks and Systems, vol 75. Springer, Singapore. https://doi.org/10.1007/978-981-13-7150-9_25
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DOI: https://doi.org/10.1007/978-981-13-7150-9_25
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