Abstract
The paper describes the architectures of various subranging flash analog-to-digital converters (ADCs) along with the proposal of a novel subranging algorithm. A comparative study of the state-of-the-art designs are made with respect to the figure of merit (FoM) and excess delay (EXD) parameter. Simulations are carried out in generic process design kit (GPDK) 45-nm technology in SPECTRE environment. The proposed subranging ADC shows an overall improvement of power by 94% per conversion cycle as compared to flash ADC. The EXD of proposed subranging ADC shows an improvement by 74% compared to binary flash ADC but however is slower than flash ADC by 34%.
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Acknowledgements
This research was supported in part by the Ministry of Electronics and Information Technology (MeitY) under Project SMDPC2SD 9(1)/2014-MDD, Government of India.
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Begum, F., Mishra, S., Najrul Islam, M., Dandapat, A. (2019). Analysis and Proposal of a Flash Subranging ADC Architecture. In: Nath, V., Mandal, J. (eds) Proceedings of the Third International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 556. Springer, Singapore. https://doi.org/10.1007/978-981-13-7091-5_26
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DOI: https://doi.org/10.1007/978-981-13-7091-5_26
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