Place and Route Optimization for High Coverage Multi-corner Multi-mode Timing Fix

Abstract

Physical design convergence becomes complicated as the number of gates is increasing with decreasing size of the transistors. Multi-corner multi-mode timing convergence is introduced to compensate for the manufacturing variation, raising the number of signoff scenarios for static timing analysis. As a result, timing violations in all scenarios need to be closed and the timing convergence process is prolonged due to the “Ping Pong Effect”. The place and route implementation tool might not have the visibility to all violations in all scenarios since not all scenarios are taken into optimization process. Some new violations might be induced due to the fixing of the other violations. Therefore, it is important to improve the visibility of the implementation tool in the actual worst slack or worst margin of all timing paths. In this paper, a methodology is proposed to create the worst-case scenario in timing slack and used in optimization process. The worst-case scenario is successfully modeled with generated worst timing margin across all the timing paths in all sign-off scenarios. With this strategy, the timing results for hold violations in terms of the worst number of slack, total number of slack and total violated path has improved by 53.2%, 95.5% and 75.9%, respectively. No significant result is recorded for setup violations. Nonetheless, it is seen as a promising approach to minimize the timing closure process.