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Architecture of Linear Massive MIMO Detection

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Massive MIMO Detection Algorithm and VLSI Architecture

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Abstract

In practical massive MIMO detection, besides the influence of the algorithm’s own characteristics on the detection results, the hardware circuits also affect the efficiency of signal detection. In Chap. 2, we have introduced four typical iteration algorithms of massive MIMO linear detection, and illustrate their advantages by comparing them with some existing linear detection algorithms. This chapter describes how to implement the four algorithms in VLSI. First, it describes the implementation of the algorithms in the hardware circuits, and the matters needing attention. Then, it introduces the optimization problems in the chip design, including how to improve the throughput of chip, and how to reduce the power consumption and area of chip. Finally, the parameters of the designed chip are compared with those of the existing linear detection algorithms, and then the comprehensive comparison results are obtained.

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Author information

Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, China

    Leibo Liu

  2. Institute of Microelectronics, Tsinghua University, Beijing, China

    Guiqiang Peng

  3. Institute of Microelectronics, Tsinghua University, Beijing, China

    Shaojun Wei

Authors
  1. Leibo Liu
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  2. Guiqiang Peng
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  3. Shaojun Wei
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Correspondence to Leibo Liu .

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© 2019 Springer Nature Singapore Pte Ltd. and Science Press, Beijing, China

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Liu, L., Peng, G., Wei, S. (2019). Architecture of Linear Massive MIMO Detection. In: Massive MIMO Detection Algorithm and VLSI Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-13-6362-7_3

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  • DOI: https://doi.org/10.1007/978-981-13-6362-7_3

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-6361-0

  • Online ISBN: 978-981-13-6362-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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