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Introduction

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Abstract

With the rapid development of the people’s demands for mobile communication in their daily life, the complex data communication and processing will become an important challenge to the future mobile communication. As the key part of the developing mobile communication technology, massive multiple-input multiple-output (MIMO) technology can improve the network capacity, enhance the network robustness and reduce the communication delay. However, as the number of antennas increases, so does the baseband processing complexity dramatically. The very large scale integration (VLSI) chip is the carrier of the massive antenna detection algorithm. The design of the massive MIMO baseband processing chip will become one of the bottlenecks in the real application of this technology, especially the design of massive MIMO detection chip with high complexity and low parallelism. The traditional MIMO detection processors, including the instruction set architecture processor (ISAP) and the application specific integrated circuit (ASIC), cannot simultaneously satisfy the three requirement indexes: energy efficiency, flexibility and scalability. In summary, the reconfigurable processor with the MIMO detection function can properly balance the requirements applied in sucs aspects as energy efficiency, flexibility and scalability, and it will be an important and promising development direction in the future.

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, China

    Leibo Liu

  2. Institute of Microelectronics, Tsinghua University, Beijing, China

    Guiqiang Peng

  3. Institute of Microelectronics, Tsinghua University, Beijing, China

    Shaojun Wei

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  1. Leibo Liu
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  2. Guiqiang Peng
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Correspondence to Leibo Liu .

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Liu, L., Peng, G., Wei, S. (2019). Introduction. In: Massive MIMO Detection Algorithm and VLSI Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-13-6362-7_1

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