Performance Analysis of Vedic Multiplier with Different Square Root BK Adders

  • Ranjith B. GowdaEmail author
  • R. M. Banakar
  • Basavaprasad
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 906)


Multiplication is the main basic operation used by many of the digital signal processor (DSP) and vector processors. DSP application repeatedly performs the operations like signal processing, filtering, processing of discrete signal data, and radar signal processing and use intensive fast Fourier transform (FFT) operations. FFT computation uses butterfly structures, where multiplication is the basic operation. DSPs have to execute a large number of instructions per second, which in turn uses so many FFT computations, and hence, the multiplication operation decides the performance of DSP. Designing a high-performance multiplier improves the overall performance of the processor. Many multiplier architectures have been proposed in the past few decades with the attractive performance, power consumption, delay, area, throughput, etc., and the most acceptable multiplier among them is the Vedic multiplier. When high performance is necessary, Vedic multiplier will be the best choice. Operation of Vedic multiplier is based on ancient Vedic mathematics. This earlier multiplier has been modified to improve the performance. There are 16 sutras for the multiplication operation in this method. These sutras are used to solve large range of multiplication problems in a natural way. This method of multiplication is based on Urdhva Triyagbhyam sutra, which means horizontal and cross-wire technique of multiplication operation. This method uses partial product generation in parallel and eliminates the unwanted steps with zero. Urdhva Triyagbhyam sutra is an efficient sutra which enhances the execution speed of the multiplier by minimizing the delay. This work describes the overall performance of the Vedic multiplier with different high-speed adders like regular square root BK adder (RSRBKA), Modified square root BK adder (MSRBKA) and proposed optimized square root BK adder (OSR-BK-A). The proposed designs are simulated and synthesized in Xilinx ISE 14.7, and the results are tabulated.


Vedic multiplier Urdhva Triyagbhyam sutra Regular square root Brent Kung adder (RSRBKA) Modified square root Brent Kung adder (MSRBKA) Optimized square root Brent Kung adder (OSRBKA) 


  1. 1.
    Wallace, C. S. (1964). A suggestion for a fast multiplier. IEEE Transactions on electronic Computers, 1, 14–17.CrossRefGoogle Scholar
  2. 2.
    Booth, A. D. (1951). A signed binary multiplication technique. The Quarterly Journal of Mechanics and Applied Mathematics, 4(2), 236–240.MathSciNetCrossRefGoogle Scholar
  3. 3.
    Bharath, J. S. S., & Tirathji, K. (1986). Vedic mathematics or sixteen simple sutras from the vedas. Varanasi (India): Motilal Banarsidas.Google Scholar
  4. 4.
    Kulkarni, S. (2007). Discrete fourier transform (DFT) by using vedic mathematics. Report, vedicmathsindia. blogspot. com.Google Scholar
  5. 5.
    Nicholas, A., Williams, K., & Pickles, J. (1984). Application of urdhava sutra. Roorkee (India): Spiritual Study Group.Google Scholar
  6. 6.
    Saokar, S. S., Banakar, R., & Siddamal, S. (2012). High speed signed multiplier for digital signal processing applications. In 2012 IEEE International Conference on Signal Processing, Computing and Control (ISPCC) (pp. 1–6). IEEE.Google Scholar
  7. 7.
    Naik, R. N., Reddy, P. S. N., & Mohan, K. M. (2013). Design of vedic multiplier for digital signal processing applications. International Journal of Engineering Trends and Technology, 4(7).Google Scholar
  8. 8.
    Thapliyal, H., & Srinivas, M. (2005). An efficient method of elliptic curve encryption using ancient Indian vedic mathematics. In 2005 48th Midwest Symposium on Circuits and Systems (pp. 826–828). IEEE.Google Scholar
  9. 9.
    Dhillon, H. S., & Mitra, A. (2008). A reduced-bit multiplication algorithm for digital arithmetic. International Journal of Computational and Mathematical Sciences, 2(2).Google Scholar
  10. 10.
    Saxena, P. (2015). Design of low power and high speed carry select adder using Brent Kung adder. International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA). IEEE.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Ranjith B. Gowda
    • 1
    Email author
  • R. M. Banakar
    • 2
  • Basavaprasad
    • 1
  1. 1.Department of ECEGovernment PolytechnicSorab, ShimogaIndia
  2. 2.Department of ECEBVB College of Engineering and TechnologyHubliIndia

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