A PVT Insensitive Low-Power Differential Ring Oscillator

  • Nishtha WadhwaEmail author
  • Pydi Ganga Bahubalindruni
  • Sujay Deb
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)


This paper presents novel low-power seven stage differential ring oscillators, which are robust against PVT variations. This work consider two different circuits, namely, current starved and negative skewed PMOS ring oscillators. Power consumption is minimized in these circuits by employing DTMOS (below 0.6 V) technique that adjusts the threshold voltage of the PMOS transistor in a dynamic way. In addition, circuit performance is made robust against PVT variations by using a self biased compensation technique. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. Circuits simulations are carried out in standard 65 nm technology with a supply voltage of 0.5 V. The worst case variation in frequency of oscillation is <4% over a temperature range of −75 \(^{\circ }\)C to 150 \(^{\circ }\)C. Process corners have resulted in 2% variation compared to the nominal, on the other hand 1% relative variation is observed when power supply is with in the range of ±5% of nominal value. Proposed current starved and skewed PMOS ring oscillators show a power consumption of 186 nW at 41 MHz and 4.2 \(\upmu \)W at 1.5 GHz, respectively, from the simulations. Both these circuits maintains the power delay product of 0.2 fJ. Given the robust performance against PVT, these circuits can find the potential applications in IoT devices.


Differential ring oscillator PVT insensitive circuits Current starved Negative skewed delay DTMOS 



The authors would like to thank everyone who helped with this work, including the project by early career research grant ECR/2017/000931.


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.IIIT-Delhi, Okhla Industrial Estate, Phase IIINew DelhiIndia

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