Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

Abstract

This work presents new flexible-architecture for maximum-a-posteriori (MAP) decoder with multi-radix modes to support various throughputs at different levels of power consumption. We have designed major internal blocks of MAP decoder using extensive steering logic to support radix-2/4/8 operating modes. These designs enable efficient clock-gating of our decoder for low-power consumption in different operating modes. This decoder-architecture is post-layout simulated in 65 nm-CMOS process and its performance analysis showed that the bit-error-rate (BER) of 10$^{-4}$ could be achieved at 5 dB. Implementation result shows that the suggested MAP decoder could achieve throughput in the range 270−810 Mbps with the corresponding power consumption range of 12.24−37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption.