Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes

  • K. S. MidhulaEmail author
  • Sarath Babu
  • John Jose
  • Sangeetha Jose
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)


It is important to design an energy efficient underlying communication framework for multicore systems. The communication framework must satisfy the requirements of NoC (Network on Chip) such as minimum latency and minimum critical path delay. Routing on multicore framework help to compute the route to which the flit wants to reach its destination. Buffered routing consumes more power and area of the chip due to the presence of in-router buffers and buffer-less routing causes more number of deflections due to unavailability of productive port on contention. Hence, design of a minimally buffered deflection router having reduced power consumption and deflection rate is critical. There are minimally buffered deflection routers, which are characterized with minimum buffering and reduced latency. Nevertheless, limitations still exist such as higher flit latency, deflection rate. In this paper, we propose a single cycle minimally buffered deflection router with a good prioritization mechanism which leads to minimum latency and reduced deflection rate than conventional minimally buffered deflection router (MinBD). This improves the quality of NoC by prioritizing aged flits which are side buffered, redirected and re-injected in the router pipeline.


Network on Chip Minimally buffered deflection router Single cycle minimally buffered deflection router 


  1. 1.
    Rantala, V., Lehtonen, T., Plosila, J.: Network on chip routing algorithms. TUCS, Technical report No 779, pp. 10–12, (2006)Google Scholar
  2. 2.
    Muralidharan, D., Muthaiah, R.: Bufferless routing algorithms: a survey. Int. J. Appl. Eng. Res. 11(6), 3811–3813 (2016)Google Scholar
  3. 3.
    Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, San Francisco (2004)Google Scholar
  4. 4.
    Peh, L.-S., Keckler, S.W., Vangal, S.: On-chip networks for multicore systems. In: Keckler, S.W., Olukotun, K., Hofstee, H.P. (eds.) Multicore Processors and Systems. ICIR, pp. 35–71. Springer, Boston (2009). Scholar
  5. 5.
    Stojanovic, I., Jovanovic, M., Djosic, S. Djordjevic, G.: Improved deflection routing method for bufferless networks-on-chip. IEEE (2013)Google Scholar
  6. 6.
    Baran, P.: On distributed communications networks. IEEE Trans. Commun. Syst. 12(1), 1–9 (1964)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Cai, Y., Mai, K., Mutlu, O.: Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. In: 16th International Symposium on Quality Electronic Design (ISQED) (2015)Google Scholar
  8. 8.
    Moscibroda, T., Mutlu, O.: A case for bufferless routing in on-chip networks. In: Proceedings of the Fourth International Symposium on Networks-on-Chip, pp. 9–16 (2010)Google Scholar
  9. 9.
    Fallin, C., Nazario, G., Yu, X., Chang, K., Ausavarungnirun, R., Mutlu, O.: Bufferless and minimally-buffered deflection routing. In: Palesi, M., Daneshtalab, M. (eds.) Routing Algorithms in Networks-on-Chip, pp. 241–275. Springer, New York (2014). Scholar
  10. 10.
    Fallin, C., Craik., Mutlu, O.: CHIPPER: a low-complexity bufferless deflection router. In: International Symposium on High Performance Computer Architecture (HPCA), pp. 144–155 (2011)Google Scholar
  11. 11.
    Fallin, C., Nazario, G., Yu, X., Chang, K., Ausavarungnirun, R., Mutlu, O.: MinBD: minimally-buffered deflection routing for energy-efficient interconnect. In: International Symposium on Networks-on-Chip (NOCS), pp. 1–10 (2012)Google Scholar
  12. 12.
    Nayak, B., Jose, J., Mutyam, M.: SLIDER: smart late injection deflection router for mesh NoCs. In: International Conference on Computer Design (ICCD), pp. 377–383 (2013)Google Scholar
  13. 13.
    Jose, J., Jonna, G.R., Radhakrishnan, R., Mutyam, M.: Minimally buffered single-cycle deflection router. In: Design, Automation and Test in Europe (DATE) (2014)Google Scholar
  14. 14.
    Michelogiannakis, G., Sanchez, G.D., Dally, W.J., Kozyrakis, C.: Evaluating bufferless flow-control for on-chip networks. In: Proceedings of the Fourth International Symposium on Networks-on-Chip, pp. 9–16 (2010)Google Scholar
  15. 15.
    Jose, J., Nayak, B., Kumar, K., Mutlu, O.: DeBAR: deflection based adaptive router with minimal buffering. In: Design, Automation and Test in Europe (DATE), pp. 1583–1588 (2013)Google Scholar
  16. 16.
    Atagoziyev, M.: Routing algorithms for on chip networks. M. Sc. Thesis, Middle East Technical University (2007)Google Scholar
  17. 17.
    Hayenga, M., Jerger, N. E., Lipasti, M.: SCARAB: a single cycle adaptive routing and bufferless routing. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42, pp. 244–254 (2009)Google Scholar
  18. 18.
    Binkert, N., et al.: The gem5 Simulator. ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1–7 (2011)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • K. S. Midhula
    • 1
    Email author
  • Sarath Babu
    • 1
  • John Jose
    • 2
  • Sangeetha Jose
    • 1
  1. 1.Government Engineering College IdukkiIdukkiIndia
  2. 2.Indian Institute of Technology GuwahatiGuwahatiIndia

Personalised recommendations