Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC

  • Ajay KhareEmail author
  • Chinmay PatilEmail author
  • Manikanta Nallamalli
  • Santanu Chattopadhyay
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)


Network-on-chip (NoC) is a paradigm shift for communication of cores in Multi-Processor System. Task mapping and priority assignment of communications is one of the critical aspects in Real-Time NoC design. Fixed priority pre-emptive arbitration is most widely used in worm-hole switched NoCs. Flow priorities, used in this arbitration, determine the network latency and are therefore crucial in guaranteeing deadline satisfaction of real-time communications. Earlier work presented in literature for flow priority assignment uses a heuristic based exhaustive search algorithm (HSA). HSA is faster but non optimal, in terms of number of priority assignments explored. Two graph-based priority assignment techniques, the GESA and the GHSA which improved on HSA also have been explored. These techniques reduce search space significantly by exploiting the interference dependencies of flows in the NoC. In this paper a search based exploratory solution to the flow priority assignment problem is proposed with a Genetic Algorithm (GA) whose evolution is guided by experimentally determined heuristics. It is compared with existing techniques and is found to give a better or equal solution in lesser computation time in most of the cases. Execution time of tasks is also considered while assigning flow priorities to make the algorithm practically applicable to real-time systems.


Real-time Network-on-chip Priority assignment Schedulability Heuristics Genetic Algorithm 


  1. 1.
    Audsley, N.C.: Optimal priority assignment and feasibility of static priority tasks with arbitrary start times. Citeseer (1991)Google Scholar
  2. 2.
    Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002)CrossRefGoogle Scholar
  3. 3.
    Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of Design Automation Conference 2001, pp. 684–689. IEEE (2001)Google Scholar
  4. 4.
    De Dinechin, B.D., Van Amstel, D., Poulhiès, M., Lager, G.: Time-critical computing on a single-chip massively parallel processor. In: Proceedings of the Conference on Design, Automation & Test in Europe, p. 97. European Design and Automation Association (2014)Google Scholar
  5. 5.
    Indrusiak, L.S.: End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. J. Syst. Architect. 60(7), 553–561 (2014)CrossRefGoogle Scholar
  6. 6.
    Indrusiak, L.S., Burns, A., Nikolic, B.: Analysis of buffering effects on hard real-time priority-preemptive wormhole networks. arXiv preprint arXiv:1606.02942 (2016)
  7. 7.
    Lee, H.G., Chang, N., Ogras, U.Y., Marculescu, R.: On-chip communication architecture exploration: a quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACM Trans. Design Autom. Electron. Syst. (TODAES) 12(3), 23 (2007)CrossRefGoogle Scholar
  8. 8.
    Leung, J.Y.T., Whitehead, J.: On the complexity of fixed-priority scheduling of periodic, real-time tasks. Perform. Eval. 2(4), 237–250 (1982)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Liu, C.L., Layland, J.W.: Scheduling algorithms for multiprogramming in a hard-real-time environment. J. ACM (JACM) 20(1), 46–61 (1973)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Liu, M., Becker, M., Behnam, M., Nolte, T.: Improved priority assignment for real-time communications in on-chip networks. In: Proceedings of the 23rd International Conference on Real Time and Networks Systems, pp. 171–180. ACM (2015)Google Scholar
  11. 11.
    Mesidis, P., Indrusiak, L.S.: Genetic mapping of hard real-time applications onto NoC-based MPSoCs-a first approach. In: 2011 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1–6. IEEE (2011)Google Scholar
  12. 12.
    Mitchell, M.: An Introduction to Genetic Algorithms. MIT Press, Cambridge (1998)zbMATHGoogle Scholar
  13. 13.
    Mohd Sayuti, M., Indrusiak, L.S., Garcia-Ortiz, A.: An optimisation algorithm for minimising energy dissipation in NoC-based hard real-time embedded systems. In: Proceedings of the 21st International Conference on Real-Time Networks and Systems, pp. 3–12. ACM (2013)Google Scholar
  14. 14.
    Nélis, V., et al.: The challenge of time-predictability in modern many-core architectures. In: 14th International Workshop on Worst-Case Execution Time Analysis (2014)Google Scholar
  15. 15.
    Ni, L.M., McKinley, P.K.: A survey of wormhole routing techniques in direct networks. Computer 26(2), 62–76 (1993)CrossRefGoogle Scholar
  16. 16.
    Racu, A., Indrusiak, L.S.: Using genetic algorithms to map hard real-time on NoC-based systems. In: 2012 7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1–8. IEEE (2012)Google Scholar
  17. 17.
    Sahu, P.K., Chattopadhyay, S.: A survey on application mapping strategies for network-on-chip design. J. Syst. Architect. 59(1), 60–76 (2013)CrossRefGoogle Scholar
  18. 18.
    Sayuti, M.N.S.M., Indrusiak, L.S.: A function for hard real-time system search-based task mapping optimisation. In: 2015 IEEE 18th International Symposium on Real-Time Distributed Computing (ISORC), pp. 66–73. IEEE (2015)Google Scholar
  19. 19.
    Shi, Z., Burns, A.: Priority assignment for real-time wormhole communication in on-chip networks. In: Real-Time Systems Symposium 2008, pp. 421–430. IEEE (2008)Google Scholar
  20. 20.
    Shi, Z., Burns, A.: Real-time communication analysis for on-chip networks with wormhole switching. In: Second ACM/IEEE International Symposium on Networks-on-Chip 2008. NoCS 2008, pp. 161–170. IEEE (2008)Google Scholar
  21. 21.
    Sparsø, J.: Design of networks-on-chip for real-time multi-processor systems-on-chip. In: 2012 12th International Conference on Application of Concurrency to System Design (ACSD), pp. 1–5. IEEE (2012)Google Scholar
  22. 22.
    Wolf, W.: Multiprocessor system-on-chip technology. IEEE Signal Process. Mag. 26(6) (2009)CrossRefGoogle Scholar
  23. 23.
    Xiong, Q., Lu, Z., Wu, F., Xie, C.: Real-time analysis for wormhole NoC: revisited and revised. In: 2016 International Great Lakes Symposium on VLSI, pp. 75–80. IEEE (2016)Google Scholar

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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Indian Institute of Technology KharagpurKharagpurIndia

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