Abstract
Simulation based investigation of Recessed Dual-Gate MISHEMT on sapphire substrate has been presented in this work using ATLAS simulation software. Various DC performance parameters such as: threshold voltage shift, drain current and transconductance has been compared for different gate combinations. Threshold voltage variation is observed to be nearly same if gate1 is recessed only or both gates are recessed. Positive shift in threshold voltage has been observed as the depth of gate recess is increased from 0 nm to 8 nm. Enhancement in negative junction depth from 10 nm to 18 nm results in the shift in threshold voltage towards positive i.e. −3.5 V to −2.45 V. This improvement in threshold voltage is due to the reduction in barrier thickness with increase in negative junction depth. DC performance has also been evaluated for the device with high-k gate dielectric such as HfO2 and TiO2 for non-recessed and recessed device. The parameters like gate oxide and work function variation results in the shift of threshold voltage from −3.5 V to 0 V in recessed Dual-Gate MISHEMT.
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References
Egawa, T., Zhao, G.Y., Ishikawa, H., Umeno, H., Jimbo, T.: Characterizations of recessed gate AlGaN/GaN HEMTs on sapphire. IEEE Trans. Electron Devices 48(3), 603–608 (2001)
Ambacher, O., et al.: Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures. J. Appl. Phys. 85(6), 3222–3233 (1999)
Palacios, T., Suh, C.S., Chakraborty, A., Keller, S., DenBaars, S.P., Mishra, U.K.: High-performance E-mode AlGaN/GaN HEMTs. IEEE Electron Device Lett. 27(6), 428–430 (2006)
Wu, J., Lu, W., Paul, K.L.: Normally-OFF AlGaN/GaN MOS-HEMT with a two-step gate recess. In: 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, pp. 594–596. IEEE (2015)
Hahn, H., et al.: First polarization-engineered compressively strained AlInGaN barrier enhancement-mode MISHFET. Semicond. Sci. Technol. 27(5), 055004 (2012)
Jessen, G.H., et al.: Gate optimization of AlGaN/GaN HEMTs using WSi, Ir, Pd, and Ni Schottky contacts. In: 25th Annual Technical Digest 2003 Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, San Diego, CA, USA, pp. 277–279. IEEE (2003)
Hilt, O., Knauer, A., Brunner, F., Bahat-Treidel, E., Würfl, J.: Normally-off AlGaN/GaN HFET with p-type Ga Gate and AlGaN buffer. In: 22nd International Symposium on Power Semiconductor Devices & IC’s (ISPSD), Hiroshima, Japan, pp. 347–350. IEEE (2010)
Gregušová, D., et al.: Adjustment of threshold voltage in AlN/AlGaN/GaN high-electron mobility transistors by plasma oxidation and Al2O3 atomic layer deposition overgrowth. Appl. Phys. Lett. 104(1), 013506 (2014)
Cai, Y., Zhou, Y., Chen, K.J., Lau, K.M.: High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment. IEEE Electron Device Lett. 26(7), 435–437 (2005)
Hahn, H., et al.: Threshold voltage engineering in GaN-based HFETs: a systematic study with the threshold voltage reaching more than 2 V. IEEE Trans. Electron Devices 62(2), 538–545 (2015)
Hasegawa, H., Akazawa, M.: Interface models and processing technologies for surface passivation and interface control in III–V semiconductor nanoelectronics. Appl. Surf. Sci. 254(24), 8005–8015 (2008)
Chong, W., et al.: Breakdown voltage and current collapse of F-plasma treated AlGaN/GaN HEMTs. J. Semicond. 35(1), 014008 (2014)
Li, W., et al.: Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability. J. Semicond. 38(7), 074001 (2017)
Yi, C., Wang, R., Huang, W., Tang, W.C.W., Lau, K.M. Chen, K.J.: Reliability of enhancement-mode AlGaN/GaN HEMTs fabricated by fluorine plasma treatment. In: IEEE International Electron Devices Meeting (IEDM 2007), Washington, DC, USA, pp. 389–392. IEEE (2007)
Hahn, H., Lükens, G., Ketteniss, N., Kalisch, H., Vescan, A.: Recessed-gate enhancement-mode AlGaN/GaN heterostructure field-effect transistors on Si with record DC performance. Appl. Phys. Express 4(11), 114102 (2011)
Chan, C.Y., Lee, T.C., Hsu, S.S., Chen, L., Lin, Y.S.: Impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors. Jpn. J. Appl. Phys. 46(2R), 478–484 (2007)
Kordoš, P., Bernat, J., Marso, M.: Impact of layer structure on performance of unpassivated AlGaN/GaN HEMT. Microelectron. J. 36(3–6), 438–441 (2005)
Gao, T., et al.: Dual-gate AlGaN/GaN MIS-HEMTs using Si3N4 as the gate dielectric. Semicond. Sci. Technol. 30(11), 115010 (2015)
Yang, L., et al.: Improvement of subthreshold characteristic of gate-recessed AlGaN/GaN transistors by using dual-gate structure. IEEE Trans. Electron Devices 64(10), 4057–4064 (2017)
Hwang, I.H., et al.: High-performance E-Mode AlGaN/GaN MIS-HEMT with dual gate insulator employing SiON and HfON. Phys. Status Solidi (A) 215, 1700650 (2018)
Silvaco ATLAS TCAD tool, version 5.24.1.R
Rzin, M., et al.: Impact of gate-drain spacing on low-frequency noise performance of in situ SiN passivated InAlGaN/GaN MIS-HEMTs. IEEE Trans. Electron Devices 64(7), 2820–2825 (2017)
Russo, S., Di Carlo, A.: Scaling issues for AlGaN/GaN HEMTs: performance optimization via devices geometry modelling (2005). arXiv preprint: https://arxiv.org/abs/cond-mat/0510049
Acknowledgement
One of the authors, Preeti Singh, would like to thank Ministry of Science and Technology, Department of Science and Technology (SR/WOS-A/ET-143/2017), Government of India and University of Delhi for providing necessary financial assistance during the course of this research work.
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Singh, P., Kumari, V., Saxena, M., Gupta, M. (2019). Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_33
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