Abstract
Due to the smaller geometries and increasing complexity, verification stage became critical phase. Development of CAD tools in every stage of design flow is necessary in technology growth. Each design quality check we can’t check manually due to its more complexity. So, automating these checks leads to less effort and more productivity. The primary focus is on introducing auto fixer for weak driver and sequential loops to get better design quality in terms of timing so that the design will operate at required frequency in all corners and providing a utility to generate stage delay by providing constant slope at the input of the stage which is useful in case of p-shift (process shift).
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Ketavanya, D., Darji, A.D. (2019). Automation of Timing Quality Checks and Optimization. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_30
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DOI: https://doi.org/10.1007/978-981-13-5950-7_30
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