A Methodology to Design Online Testable Reversible Circuits
The bottleneck of high power consumption in VLSI circuits has attracted research community to explore a new low power computing era. Reversible computing is a pioneering step towards that direction. This paper proposes a methodology to design online testable (OT) reversible circuits which can be applied to any parity preserving logic circuit. An ancilla input (L) having constant value zero is augmented with the parity preserving circuit in order to make it online testable. To demonstrate the proposed method, an online testable Fredkin gate (TFR) and an online testable Feynman double gate (TF2G) are implemented. Cascading TFR and TF2G, a master-slave (MS) D flip-flop and a dual edge triggered (DET) D flip-flop are implemented which signify the efficacy of the proposed methodology. Comparison results report that the proposed flip-flops outperform the previous designs in terms of quantum cost, number of gates used, number of constant inputs and number of garbage outputs.
KeywordsLow power computing Reversible logic Online testable (OT) circuit Sequential circuit Testable block (TB)
This entire research has been carried out under the Visvesvaraya PhD scheme which is managed by the Media Lab Asia, India and is under the supervision of the Electronics and IT Department, Ministry of Communications and IT, Government of India.
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