A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
The infrastructure of internet-of-things (IoT) and cyber-physical systems (CPS) is based on the security of communicated data. Here, lightweight cryptography plays a vital role in IoT/CPS resource-constrained environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implementations in an FPGA and ASIC. The input-output ports of the architecture are registered and datapath is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the proposed architecture is done in Xilinx Virtex-5 device in comparison to an existing design improved performance has been obtained. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology where gate equivalent (GE) of the design is 1608 GEs and area of chip is 1.55 mm2. At 100 MHz operating frequency, total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy/bit 14.018 nJ/bit, and 0.813 efficiency is obtained.
KeywordsPRESENT block cipher Lightweight cryptography VLSI architecture FPGA ASIC
The authors would like to thank Director, CSIR-CEERI, Pilani, Rajasthan, India and Ministry of Electronics and Information Technology (MeitY), Govt. of India for providing necessary resources to carry out this research. This work has been carried out under the SMDP-C2SD project, sponsored by MeitY.
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