Abstract
This paper presents the need of high-speed SRAM memory operation for minimum supply voltage. The reduction of power dissipation in memories is becoming primary importance in subthreshold region. There are several power reduction techniques which can be applied to SRAM memory cell to design low-power and energy-efficient memory. SRAM cell is designed with body biasing technique and used in the memory array to improve performance. The 32 × 32 SRAM memory array is implemented using cadence 45 nm technology. Simulation and analysis results are compared with conventional array for better performance.
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References
Mostafa H, Anis M, Elmasry M (2011) Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans Circuits Syst I 58:2859–2871
Chen G, Sylvester D, Blaauw D, Mudge T (2010) Yield-driven near-threshold SRAM design. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(11):1590
Kauppila AV, Bhuva BL, Kauppila JS, Massengill LW, Holman WT (2011) Impact of process variations on SRAM single event upsets. IEEE Trans Nucl Sci 58(3):834
Kim TT-H, Ba NL (2014) Design of a temperature-aware low-voltage SRAM with self-adjustable sensing margin enhancement for high-temperature applications up to 300 °C. IEEE J Solid-State Circuits 49(11):2534
Suthar R, Pande KS, Murty NS (2017) Leakage reduction in DT8T SRAM cell using body biasing technique. In: IEEE international symposium on nanoelectronic and information systems, pp 1–5
Shakir T, Sachdev M (2014) A body-bias based current sense amplifier for high-speed low-power embedded SRAMS, pp 444–448
Hokimoto S, Ishihara T, Onodera H (2016) Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing, pp 1–6
Zheng N, Mazumder P (2017) Modeling and mitigation of static noise margin variation is subthreshold SRAM cells. IEEE Trans Circuits Syst I 64:2726–2736
Khayatzadeh M, Lian Y (2013) Average-8T differential-sensing subthreshold SRAM with bit interleaving and 1 k bits per bitline. IEEE Trans Very Large Scale Integr (VLSI) Syst, 1–12
Jiang C, Zhang D, Zhang S, Wang H, Zhuang Z (2017) A yield-driven near-threshold 8-T negative bit-line scheme, pp 315–318
Kim TT, Le Ba N (2013) A low voltage 8-T SRAM with PVT-tracking bitline sensing margin enhancement for high operating temperature (up to 300 °C), pp 233–236
Calimera A, Macii A, Macii E, Poncino M (2012) Design techniques and architectures for low-leakage SRAMS. IEEE Trans Circuits Syst I 59:1992–2007
Gupta SK, Raychowdhury A, Roy K (2010) Digital computation in subthreshold region for ultralow-power operation: a device–circuit–architecture codesign perspective. IEEE 98(2):160
Sharma CK, Chandel R (2014) Analysis of SRAM cell designs for low power applications. In: International conference for convergence of technology, p 1
Indumathi G, Aarthi alias Ananthakirupa VPMB (2014) Energy optimization techniques on SRAM: a survey. In: 2014 international conference on communication and network technologies (ICCNT), p 216
Sharan S, Chandra A, Goel N, Kumar A (2016) Comparison of 6T-SRAM cell designs using DTMOS and VTMOS for low power applications. In: IEEE international conference on power electronics, intelligent control and energy systems (ICPEICES-2016), pp 1–5
Torrens G, Alorda B, Carmona C, Malagón-Periánez D, Segura J, Bota SA (2017) A 65-nm reliable 6T CMOS SRAM cell with minimum size transistors. IEEE Trans Emerg Top Comput 1–9
Toh SO, Guo Z, Liu T-JK, Nikolić B (2011) Characterization of dynamic SRAM stability in 45 nm CMOS. IEEE J Solid-State Circuits 46(11):2702
Vashisht G, Pahuja H, Singh B, Panday S (2016) Design and comparative analysis of low power 64 bit SRAM and its peripherals using power reduction techniques
Kumar SS, Soni G (2015) Power, energy and SNM optimization of 6TSRAM cell using power gating technique. In: 2015 fifth international conference on communication systems and network technologies, p 889
Zheng N, Mazumder P (2017) Modeling and mitigation of static noise margin variation in subthreshold SRAM cells. IEEE Trans Circuits Syst I: Regul Pap 64(10):2726–2736
Saeidi R, Sharifkhani M, Hajsadeghi K (2014) Statistical analysis of read static noise margin for near/sub-threshold SRAM cell. IEEE Trans Circuits Syst I: Regul Pap 61(12):3386
Saeidi R, Sharifkhani M, Hajsadeghi K (2014) A subthreshold symmetric SRAM cell with high read stability. IEEE Trans Circuits Syst II: Express Briefs 61(1):26
Ruchi Sudeb Dasgupta (2018) Compact analytical model to extract write static noise margin (WSNM) for SRAM cell at 45 nm and 65 nm nodes. IEEE Trans Semicond Manuf 31(1):1–8
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Kalyani, P., Madhavi Latha, M., Chandra Sekhar, P. (2019). Energy-Efficient SRAM Cell Design with Body Biasing. In: Saini, H., Singh, R., Kumar, G., Rather, G., Santhi, K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 65. Springer, Singapore. https://doi.org/10.1007/978-981-13-3765-9_39
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DOI: https://doi.org/10.1007/978-981-13-3765-9_39
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