Abstract
Low power and high speed are critical design issues in the field of microprocessor design. Arithmetic and logic unit (ALU) is one of the most power and delay consuming elements of microprocessor. Conventional approach to design an ALU of microprocessor uses two different units to perform arithmetic and logical operation, respectively. Arithmetic unit is designed with adders while logical unit with logic gates. Adders are selected as per the application requirement based on VLSI matrices. In this paper, we present configurable ALU that improves performance in terms of speed and power. To achieve the objective, configurable ALU uses two adders to perform the same task. We also present a method to increase the number of logical operations. In the proposed design, eight arithmetic and eight logical operations are performed with 4-bit binary data. The proposed design is verified using Xilinx ISE 14.7 design suite and synthesized by genus synthesis solution of cadence at GDPK-45 nm technology. The proposed work offers saving up to 21.196%, up to 20.312%, and up to 6.288% in power, area, and delay, respectively.
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Kabra, N.K., Patel, Z.M. (2019). Low-Power and High-Speed Configurable Arithmetic and Logic Unit. In: Saini, H., Singh, R., Kumar, G., Rather, G., Santhi, K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 65. Springer, Singapore. https://doi.org/10.1007/978-981-13-3765-9_37
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DOI: https://doi.org/10.1007/978-981-13-3765-9_37
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