Abstract
In this paper, error detector circuits have been designed and compared with each other in different aspects. The different architecture has been simulated and verified in Virtuoso tool. For circuit verification, GDI technique and static CMOS technique have been used. As we know VLSI technology is used for low power consumption, less size, less delay, etc. These are critical design issues in most modern embedded system. As we have several techniques to check error in the circuit like using Hamming code method, parity generate method. In this paper, a new technique is proposed named as “error detection using counting technique” with that number of zeros or number of ones can be counted. It increases the chances of finding errors. This technique is compared with other techniques such as even parity generator and odd parity generator. The proposed technique is designed and compared using sub-micron technology in Cadence software.
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Behind every achievement, there is unfathomable sea of gratitude to those who supported it and without whom it would ever have been a successful one. I am thankful to my Principal and Head of Department for their support and encouragement. This paper is dedicated to my beloved son.
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Bhardwaj, K.K., Swapna Rani, T. (2019). Error Detection Using Counting Technique in Low-Power VLSI. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 900. Springer, Singapore. https://doi.org/10.1007/978-981-13-3600-3_42
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DOI: https://doi.org/10.1007/978-981-13-3600-3_42
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