FPGA Implementation of Coding for Minimizing Delay and Power in SOC Interconnects

  • N. ChintaiahEmail author
  • G. Umamaheswara Reddy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 898)


In this paper, the bus encoding technique is introduced to reduce the number of transitions. The data word transmission on an on-chip bus causes the switching of data bits on the bus wires. This switching charges and discharges the capacitance associated with the wires and consequently causes dynamic power dissipation and increase in delay. A substantial amount of power is dissipated from buses compared with the power dissipation of the remaining circuit. The data bits sent through these buses should be encoded to decrease the switching activity, thereby reducing the power consumption and delay of the buses. In this approach, encoding is widely used to reduce the number of transitions. The encoder comprises four subdivisions, and the average power conserved was 10.17%. Overall, the average delay is decreased by 4.5%. Therefore, more amount of average power is conserved, and the delay is shortened.


Crosstalk Encoder Path delay Even–odd inversion Upper–lower inversion 


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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringSri Venkateswara UniversityTirupatiIndia

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