9T and 8T Full Subtractor Design Using Modified GDI and 3T XOR Technique
Circuit designing is an emerging field and as per the recent trend it evolves digital devices in use—portable as well as smaller in size. This paper proposes two designs of full subtractor circuit based upon eight and nine transistors demonstrating low power consumption and high-speed switching. The combination of 3T XOR and modified gate diffusion input (M-GDI) technique has been implied to realize the circuits. The circuit realization and simulations have been performed using DSCH 3.5. The design has been further verified and simulated in Xilinx ISE 14.7 environment, coded using Verilog HDL.
KeywordsCircuit Low power High speed Subtractor Gate diffusion input (GDI) Modified gate diffusion input (M-GDI) 3T XOR DSCH 3.5 Verilog HDL
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